| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | tlv320adcx140.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-t
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| H A D | ti,tlv320adcx140.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
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| H A D | cs35l34.txt | 5 - compatible : "cirrus,cs35l34"
7 - reg : the I2C address of the device for I2C.
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-vtge-millivolt : Boost Voltage Value. Configures the boost
17 - cirrus,boost-nanohenry: Inductor value for boost converter. The value is
22 - reset-gpios: GPIO used to reset the amplifier.
24 - interrupts : IRQ line info CS35L34.
25 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
28 - cirrus,boost-peak-milliamp : Boost converter peak current limit in mA. The
32 - cirrus,i2s-sdinloc : ADSP SDIN I2S channel location. Indicates whether the
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| /freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | gpio-poweroff.txt | 3 The driver supports both level triggered and edge triggered power off.
9 When the power-off handler is called, the gpio is configured as an
11 condition. This will also cause an inactive->active edge condition, so
12 triggering positive edge triggered power off. After a delay of 100ms,
13 the GPIO is set to inactive, thus causing an active->inactive edge,
14 triggering negative edge triggered power off. After another 100ms
19 - compatible : should be "gpio-poweroff".
20 - gpios : The GPIO to set high/low, see "gpios property" in
22 low to power down the board set it to "Active Low", otherwise set
26 - input : Initially configure the GPIO line as an input. Only reconfigure
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| H A D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
24 low to reset the board set it to "Active Low", otherwise set
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| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restar
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| /freebsd/sys/dev/ic/ |
| H A D | via6522reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
38 #define REG_T1CL 4 /* T1 low-order latch/low-order counter */
39 #define REG_T1CH 5 /* T1 high-order counter */
40 #define REG_T1LL 6 /* T1 low-order latches */
41 #define REG_T1LH 7 /* T1 high-order latches */
42 #define REG_T2CL 8 /* T2 low-order latch/low-order counter */
43 #define REG_T2CH 9 /* T2 high-order counter */
48 #define REG_IER 14 /* Interrupt-enable register */
54 #define ACR_SR_DIR 0x4 /* Bit for shift-register direction 1=out */
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | brcm,kona-gpio.txt | 9 GPIO controller only supports edge, not level, triggering of interrupts.
12 -------------------
14 - compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
15 - reg: Physical base address and length of the controller's registers.
16 - interrupts: The interrupt outputs from the controller. There is one GPIO
21 - #gpio-cells: Should be <2>. The first cell is the pin number, the second
23 - bit 0 specifies polarity (0 for normal, 1 for inverted)
24 See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
25 - #interrupt-cells: Should be <2>. The first cell is the GPIO number. The
28 - trigger type (bits[1:0]):
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| H A D | cavium-octeon-gpio.txt | 4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
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| H A D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
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| H A D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
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| H A D | gpio-zynq.txt | 2 -------------------------------------------
5 - #gpio-cells : Should be two
6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or
10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
11 or "xlnx,pmc-gpio-1.0
12 - clocks : Clock specifier (see clock bindings for details)
13 - gpio-controller : Marks the device node as a GPIO controller.
14 - interrupts : Interrupt specifier (see interrupt bindings for
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| H A D | gpio-omap.txt | 4 - compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8 - reg : Physical base address of the controller and length of memory mapped
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two.
12 - first cell is the pin number
13 - second cell is used to specify optional parameters (unused)
14 - interrupt-controller: Mark the device node as an interrupt controller.
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| H A D | gpio-vf610.txt | 8 - compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
11 - reg : The first reg tuple represents the PORT module, the second tuple
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
18 1 = active low
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
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| H A D | gpio-xlp.txt | 10 -------------------
12 - compatible: Should be one of the following:
13 - "netlogic,xlp832-gpio": For Netlogic XLP832
14 - "netlogic,xlp316-gpio": For Netlogic XLP316
15 - "netlogic,xlp208-gpio": For Netlogic XLP208
16 - "netlogic,xlp980-gpio": For Netlogic XLP980
17 - "netlogic,xlp532-gpio": For Netlogic XLP532
18 - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64
19 - reg: Physical base address and length of the controller's registers.
20 - #gpio-cells: Should be two. The first cell is the pin number and the second
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LazyCallGraph.cpp | 1 //===- LazyCallGraph.cpp - Analysis of a Module's call graph --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
41 Edge::Kind EK) { in insertEdgeInternal()
46 void LazyCallGraph::EdgeSequence::setEdgeKind(Node &TargetN, Edge::Kind EK) { in setEdgeKind()
47 Edges[EdgeIndexMap.find(&TargetN)->second].setKind(EK); in setEdgeKind()
55 Edges[IndexMapI->second] = Edge(); in removeEdgeInternal()
60 static void addEdge(SmallVectorImpl<LazyCallGraph::Edge> &Edges, in addEdge()
62 LazyCallGraph::Node &N, LazyCallGraph::Edge::Kind EK) { in addEdge()
67 Edges.emplace_back(LazyCallGraph::Edge(N, EK)); in addEdge()
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| /freebsd/sys/contrib/device-tree/Bindings/display/panel/ |
| H A D | panel-timing.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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| H A D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
30 core_intc: core-interrupt-controller {
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| H A D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
22 - reg: Should contain AIC registers location and length
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| H A D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/ |
| H A D | riscv.h | 1 //===-- riscv.h - Generic JITLink riscv edge kinds, utilities -*- C++ -*-===//
5 // SPDX-License-Identifie
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| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | fsl,qe-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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| /freebsd/contrib/byacc/ |
| H A D | lalr.c | 77 for (sp = first_state; sp; sp = sp->next) in set_state_table()
78 state_table[sp->number] = sp; in set_state_table()
87 for (sp = first_state; sp; sp = sp->next) in set_accessing_symbol()
88 accessing_symbol[sp->number] = sp->accessing_symbol; in set_accessing_symbol()
97 for (sp = first_shift; sp; sp = sp->next) in set_shift_table()
98 shift_table[sp->number] = sp; in set_shift_table()
107 for (rp = first_reduction; rp; rp = rp->next) in set_reduction_table()
108 reduction_table[rp->number] = rp; in set_reduction_table()
153 k += rp->nreds; in initialize_LA()
167 for (j = 0; j < rp->nreds; j++) in initialize_LA()
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | icpdas-lp8841-spi-rtc.txt | 1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
6 The device uses the standard MicroWire half-duplex transfer timing.
7 Master output is set on low clock and sensed by the RTC on the rising
8 edge. Master input is set by the RTC on the trailing edge and is sensed
9 by the master on low clock.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
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