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/linux/drivers/cxl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 The CXL specification defines a "CXL memory device" sub-class in the
30 memory to be mapped into the system address map (Host-managed Device
72 (https://www.computeexpresslink.org/spec-landing). The CXL core
99 known as HDM "Host-managed Device Memory".
119 bool "CXL: EDAC Memory Features"
123 depends on EDAC >= CXL_BUS
125 The CXL EDAC memory feature is optional and allows host to
126 control the EDAC memory features configurations of CXL memory
138 The CXL EDAC scrub control is optional and allows host to
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/linux/Documentation/driver-api/
H A Dedac.rst1 Error Detection And Correction (EDAC) Devices
4 Main Concepts used at the EDAC subsystem
5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
46 lockstep is enabled, the cacheline is doubled, but it generally brings
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
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/linux/drivers/edac/
H A Dnpcm_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #define EDAC_MOD_NAME "npcm-edac"
106 struct priv_data *priv = mci->pvt_info; in handle_ce()
111 pdata = priv->pdata; in handle_ce()
112 regmap_read(npcm_regmap, pdata->ctl_ce_addr_l, &val_l); in handle_ce()
113 if (pdata->chip == NPCM8XX_CHIP) { in handle_ce()
114 regmap_read(npcm_regmap, pdata->ctl_ce_addr_h, &val_h); in handle_ce()
115 val_h &= pdata->ce_addr_h_mask; in handle_ce()
119 regmap_read(npcm_regmap, pdata->ctl_ce_data_l, &val_l); in handle_ce()
120 if (pdata->chip == NPCM8XX_CHIP) in handle_ce()
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H A Da72_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cortex A72 EDAC L1 and L2 cache error detection
20 #define DRVNAME "a72-edac"
51 u64 cpu_mesr = mesr->cpu_mesr; in report_errors()
52 u64 l2_mesr = mesr->l2_mesr; in report_errors()
61 str = "L1-I Tag RAM"; in report_errors()
64 str = "L1-I Data RAM"; in report_errors()
67 str = "L1-D Tag RAM"; in report_errors()
70 str = "L1-D Data RAM"; in report_errors()
106 mesr->cpu_mesr = read_sysreg_s(SYS_CPUMERRSR_EL1); in read_errors()
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H A Dcpc925_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
13 #include <linux/edac.h>
34 #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr))
37 * EDAC device names for the error detections of
50 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
139 #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/
141 #define MSCR_SI_SHIFT 16 /* si - bit8:15*/
217 ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */
246 LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */
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H A Dzynqmp_edac.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/edac.h>
70 #define EDAC_DEVICE "ZynqMP-OCM"
73 * struct ecc_error_info - ECC error log information
75 * @fault_lo: Generated fault data (lower 32-bit)
76 * @fault_hi: Generated fault data (upper 32-bit)
85 * struct ecc_status - ECC status information to report
99 * struct edac_priv - OCM private instance data
125 * get_error_info - Get the current ECC error info
136 p->ce_cnt++; in get_error_info()
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H A Damd76x_edac.c9 * http://www.anime.net/~goemon/linux-ecc/
19 #include <linux/edac.h>
33 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
38 * 15:14 SERR enabled: x1=ue 1x=ce
40 * 12 diag: disabled, enabled
49 * 31:26 clock disable 5 - 0
57 * 17:16 cycles-per-refresh
59 * 7:0 x4 mode enable 7 -
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H A Darmada_xp_edac.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/edac.h>
12 #include <asm/hardware/cache-l2x0.h>
13 #include <asm/hardware/cache-aurora-l2.h>
19 /************************ EDAC MC (DDR RAM) ********************************/
88 if (drvdata->width == 8) { in axp_mc_calc_address()
90 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
100 } else if (drvdata->width == 4) { in axp_mc_calc_address()
102 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
114 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
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H A Dsynopsys_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
9 #include <linux/edac.h>
268 * struct ecc_error_info - ECC error log information.
288 * struct synps_ecc_status - ECC status information to report.
302 * struct synps_edac_priv - DDR memory controller private instance data.
342 * struct synps_platform_data - synps platform data structure.
344 * @get_error_info: Get EDAC error info.
347 * @get_mem_info: Get EDAC memory info
362 * zynq_get_error_info - Get the current ECC error info.
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H A Dversal_edac.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/edac.h>
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
149 * struct ecc_error_info - ECC error log information.
195 * struct ecc_status - ECC status information to report.
209 * struct edac_priv - DDR memory controller private instance data.
255 ddrmc_base = priv->ddrmc_baseaddr; in get_ce_error_info()
256 p = &priv->stat; in get_ce_error_info()
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H A Docteon_edac-lmc.c7 * written by Ralf Baechle <ralf@linux-mips.org>
16 #include <linux/edac.h>
20 #include <asm/octeon/cvmx-lmcx-defs.h>
44 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx)); in octeon_lmc_edac_poll()
47 fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx)); in octeon_lmc_edac_poll()
56 -1, -1, -1, msg, ""); in octeon_lmc_edac_poll()
57 cfg0.s.sec_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
63 -1, -1, -1, msg, ""); in octeon_lmc_edac_poll()
64 cfg0.s.ded_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
68 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64); in octeon_lmc_edac_poll()
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H A Di82975x_edac.c16 #include <linux/edac.h>
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
37 * 31:7 128 byte cache-line address
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
69 NOTE: Only ONE of the three must be enabled
76 * 9 non-DRAM lock error (ndlock)
105 * 31:14 Base Addr of 16K memory-mapped
108 * 0 mem-mappe
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H A Dversalnet_edac.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/edac.h>
76 * struct ecc_error_info - ECC error log information.
124 * struct ecc_status - ECC status information to report.
138 * struct mc_priv - DDR memory controller private instance data.
229 p = &priv->stat; in get_ddr_info()
232 p->channel = 1; in get_ddr_info()
234 p->channel = 0; in get_ddr_info()
239 p->ceinfo[0].i = reglo | (u64)reghi << 32; in get_ddr_info()
241 p->ueinfo[0].i = reglo | (u64)reghi << 32; in get_ddr_info()
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H A Di3200_edac.c3 * Copyright (C) 2008-2009 Akamai Technologies, Inc.
14 #include <linux/edac.h>
18 #include <linux/io-64-nonatomic-lo-hi.h>
29 /* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
55 * 9 LOCK to non-DRAM Memory Flag (LCKF)
59 * 1 Multi-bi
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H A De752x_edac.c10 * https://www.intel.in/content/www/in/en/chipsets/e7525-memory-controller-hub-datasheet.html
26 #include <linux/edac.h>
33 static int sysbus_parity = -1;
77 /* E752X register addresses - device 0 function 0 */
115 /* E752X register addresses - device 0 function 1 */
173 /* 3100 IMCH specific register addresses - device 0 function 1 */
179 /* ICH5R register addresses - devic
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H A Di5100_edac.c9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
12 * The intel 5100 has two independent channels. EDAC core currently
13 * can not reflect this configuration so instead the chip-select
27 #include <linux/edac.h>
70 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
82 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
85 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
86 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
127 return a & ((1 << 8) - 1); in i5100_spddata_data()
133 return ((dti & ((1 << 4) - in i5100_spdcmd_create()
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/linux/Documentation/firmware-guide/acpi/apei/
H A Deinj.rst1 .. SPDX-License-Identifier: GPL-2.0
15 which shows that the BIOS is exposing an EINJ table - it is the
28 To use EINJ, make sure the following are options enabled in your kernel
43 - available_error_type
51 0x00000002 Processor Uncorrectable non-fatal
54 0x00000010 Memory Uncorrectable non-fatal
57 0x00000080 PCI Express Uncorrectable non-fatal
60 0x00000400 Platform Uncorrectable non-fatal
70 - error_type
75 - error_inject
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/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heine
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/linux/drivers/cxl/core/
H A Dedac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CXL EDAC memory feature driver.
5 * Copyright (c) 2024-2025 HiSilicon Limited.
7 * - Supports functions to configure EDAC features of the
9 * - Registers with the EDAC device subsystem driver to expose
15 #include <linux/edac.h>
27 #define CXL_SCRUB_NO_REGION -1
41 * See CXL spec rev 3.2 @8.2.10.9.11.1 Table 8-222 Device Patrol Scrub Control
51 * See CXL spec rev 3.2 @8.2.10.9.11.1 Table 8-223 Device Patrol Scrub Control
85 return -ENOMEM; in cxl_mem_scrub_get_attrbs()
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/linux/drivers/acpi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
20 Linux requires an ACPI-compliant platform (hardware/firmware),
21 and assumes the presence of OS-directed configuration and power
27 the Plug-and-Play BIOS specification (PnP BIOS), the
37 ACPI is an open industry specification originally co-developed by
38 Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. Currently,
73 Enable in-kernel debugging of AML facilities: statistics,
131 This option enables a DMI-based quirk for the above Dell machine (so
193 performs user-defined actions such as shutting down the system.
194 This is necessary for software-controlled poweroff.
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/linux/arch/powerpc/sysdev/
H A Dfsl_pci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
11 * Roy Zang <tie-fei.zang@freescale.com>
12 * MPC83xx PCI-Express support:
20 #include <linux/fsl/edac.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/ppc-pci.h>
39 #include <asm/ppc-opcode.h>
60 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in quirk_fsl_pcie_early()
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt1 ACPI ACPI support is enabled.
2 AGP AGP (Accelerated Graphics Port) is enabled.
3 ALSA ALSA sound support is enabled.
4 APIC APIC support is enabled.
5 APM Advanced Power Management support is enabled.
6 APPARMOR AppArmor support is enabled.
7 ARM ARM architecture is enabled.
8 ARM64 ARM64 architecture is enabled.
9 CLK Common clock infrastructure is enabled.
10 CMA Contiguous Memory Area support is enabled
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/linux/arch/x86/kernel/cpu/mce/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
87 .bootlog = -1,
88 .monarch_timeout = -1
98 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
114 * CPU/chipset specific EDAC code can register a notifier call here to print
115 * MCE errors in a human-readable form.
121 m->cpui in mce_prep_record_common()
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