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/linux/drivers/cxl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 The CXL specification defines a "CXL memory device" sub-class in the
30 memory to be mapped into the system address map (Host-managed Device
72 (https://www.computeexpresslink.org/spec-landing). The CXL core
99 known as HDM "Host-managed Device Memory".
119 bool "CXL: EDAC Memory Features"
123 depends on EDAC >= CXL_BUS
125 The CXL EDAC memory feature is optional and allows host to
126 control the EDAC memory features configurations of CXL memory
138 The CXL EDAC scrub control is optional and allows host to
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/linux/drivers/edac/
H A Daltera_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
17 #include <linux/mfd/altera-sysmgr.h>
77 /*********************** EDAC Memory Controller Functions ****************/
79 /* The SDRAM controller uses the EDAC Memory Controller framework. */
84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; in altr_sdram_mc_err_handler()
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H A Dnpcm_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #define EDAC_MOD_NAME "npcm-edac"
106 struct priv_data *priv = mci->pvt_info; in handle_ce()
111 pdata = priv->pdata; in handle_ce()
112 regmap_read(npcm_regmap, pdata->ctl_ce_addr_l, &val_l); in handle_ce()
113 if (pdata->chip == NPCM8XX_CHIP) { in handle_ce()
114 regmap_read(npcm_regmap, pdata->ctl_ce_addr_h, &val_h); in handle_ce()
115 val_h &= pdata->ce_addr_h_mask; in handle_ce()
119 regmap_read(npcm_regmap, pdata->ctl_ce_data_l, &val_l); in handle_ce()
120 if (pdata->chip == NPCM8XX_CHIP) in handle_ce()
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H A Da72_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cortex A72 EDAC L1 and L2 cache error detection
20 #define DRVNAME "a72-edac"
51 u64 cpu_mesr = mesr->cpu_mesr; in report_errors()
52 u64 l2_mesr = mesr->l2_mesr; in report_errors()
61 str = "L1-I Tag RAM"; in report_errors()
64 str = "L1-I Data RAM"; in report_errors()
67 str = "L1-D Tag RAM"; in report_errors()
70 str = "L1-D Data RAM"; in report_errors()
106 mesr->cpu_mesr = read_sysreg_s(SYS_CPUMERRSR_EL1); in read_errors()
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H A Dxgene_edac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * APM X-Gene SoC EDAC (error detection and correction)
11 #include <linux/edac.h>
67 static void xgene_edac_pcp_rd(struct xgene_edac *edac, u32 reg, u32 *val) in xgene_edac_pcp_rd() argument
69 *val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_rd()
72 static void xgene_edac_pcp_clrbits(struct xgene_edac *edac, u32 reg, in xgene_edac_pcp_clrbits() argument
77 spin_lock(&edac->lock); in xgene_edac_pcp_clrbits()
78 val = readl(edac->pcp_csr + reg); in xgene_edac_pcp_clrbits()
80 writel(val, edac->pcp_csr + reg); in xgene_edac_pcp_clrbits()
81 spin_unlock(&edac->lock); in xgene_edac_pcp_clrbits()
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H A Dzynqmp_edac.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/edac.h>
70 #define EDAC_DEVICE "ZynqMP-OCM"
73 * struct ecc_error_info - ECC error log information
75 * @fault_lo: Generated fault data (lower 32-bit)
76 * @fault_hi: Generated fault data (upper 32-bit)
85 * struct ecc_status - ECC status information to report
99 * struct edac_priv - OCM private instance data
125 * get_error_info - Get the current ECC error info
136 p->ce_cnt++; in get_error_info()
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H A Dcpc925_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
13 #include <linux/edac.h>
34 #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr))
37 * EDAC device names for the error detections of
50 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
139 #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/
141 #define MSCR_SI_SHIFT 16 /* si - bit8:15*/
217 ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */
246 LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */
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H A Darmada_xp_edac.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/edac.h>
12 #include <asm/hardware/cache-l2x0.h>
13 #include <asm/hardware/cache-aurora-l2.h>
19 /************************ EDAC MC (DDR RAM) ********************************/
88 if (drvdata->width == 8) { in axp_mc_calc_address()
90 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
100 } else if (drvdata->width == 4) { in axp_mc_calc_address()
102 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
114 if (drvdata->cs_addr_sel[cs]) in axp_mc_calc_address()
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H A Dsynopsys_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
9 #include <linux/edac.h>
268 * struct ecc_error_info - ECC error log information.
288 * struct synps_ecc_status - ECC status information to report.
302 * struct synps_edac_priv - DDR memory controller private instance data.
342 * struct synps_platform_data - synps platform data structure.
344 * @get_error_info: Get EDAC error info.
347 * @get_mem_info: Get EDAC memory info
362 * zynq_get_error_info - Get the current ECC error info.
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H A Dversal_edac.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/edac.h>
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
149 * struct ecc_error_info - ECC error log information.
195 * struct ecc_status - ECC status information to report.
209 * struct edac_priv - DDR memory controller private instance data.
255 ddrmc_base = priv->ddrmc_baseaddr; in get_ce_error_info()
256 p = &priv->stat; in get_ce_error_info()
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H A Docteon_edac-lmc.c7 * written by Ralf Baechle <ralf@linux-mips.org>
16 #include <linux/edac.h>
20 #include <asm/octeon/cvmx-lmcx-defs.h>
44 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx)); in octeon_lmc_edac_poll()
47 fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx)); in octeon_lmc_edac_poll()
56 -1, -1, -1, msg, ""); in octeon_lmc_edac_poll()
57 cfg0.s.sec_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
63 -1, -1, -1, msg, ""); in octeon_lmc_edac_poll()
64 cfg0.s.ded_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
68 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64); in octeon_lmc_edac_poll()
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H A Dversalnet_edac.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/edac.h>
76 * struct ecc_error_info - ECC error log information.
124 * struct ecc_status - ECC status information to report.
138 * struct mc_priv - DDR memory controller private instance data.
229 p = &priv->stat; in get_ddr_info()
232 p->channel = 1; in get_ddr_info()
234 p->channel = 0; in get_ddr_info()
239 p->ceinfo[0].i = reglo | (u64)reghi << 32; in get_ddr_info()
241 p->ueinfo[0].i = reglo | (u64)reghi << 32; in get_ddr_info()
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H A Damd64_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * Set by command line parameter. If BIOS has enabled the ECC, this override is
12 * cleared to prevent re-enabling the hardware by this driver.
21 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
33 /* Per-node stuff */
41 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
83 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
96 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
108 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg); in f15h_select_dct()
109 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
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H A Die31200_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel E3-1200
6 * Support for the E3-1200 processor family. Heavily based on previous
7 * Intel EDAC drivers.
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
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H A Dpnd2_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/edac.h>
35 #include <asm/intel-family.h>
80 u8 enabled; member
112 #define SELECTOR_DISABLED (-1)
130 * side-band mailbox style interface in a hidden PCI device
168 ret = -EAGAIN; in _apl_rd_reg()
179 if (retries-- == 0) { in _apl_rd_reg()
180 ret = -EBUSY; in _apl_rd_reg()
249 return -ENODEV; in dnv_rd_reg()
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H A Dsb_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
17 #include <linux/edac.h>
23 #include <asm/intel-family.h>
69 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
70 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
71 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
72 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
73 0x100, 0x108, 0x110, 0x118, /* 20-23 */
106 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
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/linux/Documentation/driver-api/
H A Dedac.rst1 Error Detection And Correction (EDAC) Devices
4 Main Concepts used at the EDAC subsystem
5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
46 lockstep is enabled, the cacheline is doubled, but it generally brings
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
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/linux/Documentation/firmware-guide/acpi/apei/
H A Deinj.rst1 .. SPDX-License-Identifier: GPL-2.0
15 which shows that the BIOS is exposing an EINJ table - it is the
28 To use EINJ, make sure the following are options enabled in your kernel
43 - available_error_type
51 0x00000002 Processor Uncorrectable non-fatal
54 0x00000010 Memory Uncorrectable non-fatal
57 0x00000080 PCI Express Uncorrectable non-fatal
60 0x00000400 Platform Uncorrectable non-fatal
70 - error_type
75 - error_inject
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/linux/include/linux/
H A Dedac.h2 * Generic EDAC defs
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
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/linux/Documentation/core-api/real-time/
H A Dhardware.rst1 .. SPDX-License-Identifier: GPL-2.0
18 -----------------------
32 project (https://www.open-mpi.org/projects/hwloc/) can visualize the hierarchy.
52 c2c tool can help identify cache-to-cache issues, where multiple CPU
56 --------------
58 Real-time systems often need to access hardware directly to perform their work.
76 requirements of certain real-time use cases.
79 instance, PCIe with Active State Power Management (ASPM) enabled can suspend
82 is not limited to PCIe; internal buses within a System-on-Chip (SoC) can also be
86 --------------
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/linux/drivers/net/phy/qcom/
H A Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
25 #include <dt-bindings/net/qca-ar803x.h>
47 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
60 * By default the PLL is only enabled if there is a link. Otherwise
63 * enabled.
119 /* MDAC and EDAC values for short cable length */
241 context->bmcr = phy_read(phydev, MII_BMCR); in at803x_context_save()
242 context->advertise = phy_read(phydev, MII_ADVERTISE); in at803x_context_save()
243 context->control1000 = phy_read(phydev, MII_CTRL1000); in at803x_context_save()
244 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); in at803x_context_save()
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/linux/drivers/cxl/core/
H A Dedac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CXL EDAC memory feature driver.
5 * Copyright (c) 2024-2025 HiSilicon Limited.
7 * - Supports functions to configure EDAC features of the
9 * - Registers with the EDAC device subsystem driver to expose
15 #include <linux/edac.h>
27 #define CXL_SCRUB_NO_REGION -1
41 * See CXL spec rev 3.2 @8.2.10.9.11.1 Table 8-222 Device Patrol Scrub Control
51 * See CXL spec rev 3.2 @8.2.10.9.11.1 Table 8-223 Device Patrol Scrub Control
85 return -ENOMEM; in cxl_mem_scrub_get_attrbs()
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/linux/drivers/acpi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
20 Linux requires an ACPI-compliant platform (hardware/firmware),
21 and assumes the presence of OS-directed configuration and power
27 the Plug-and-Play BIOS specification (PnP BIOS), the
37 ACPI is an open industry specification originally co-developed by
38 Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba. Currently,
73 Enable in-kernel debugging of AML facilities: statistics,
131 This option enables a DMI-based quirk for the above Dell machine (so
193 performs user-defined actions such as shutting down the system.
194 This is necessary for software-controlled poweroff.
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt1 ACPI ACPI support is enabled.
2 AGP AGP (Accelerated Graphics Port) is enabled.
3 ALSA ALSA sound support is enabled.
4 APIC APIC support is enabled.
5 APM Advanced Power Management support is enabled.
6 APPARMOR AppArmor support is enabled.
7 ARM ARM architecture is enabled.
8 ARM64 ARM64 architecture is enabled.
9 CLK Common clock infrastructure is enabled.
10 CMA Contiguous Memory Area support is enabled.
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/linux/arch/powerpc/sysdev/
H A Dfsl_pci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
11 * Roy Zang <tie-fei.zang@freescale.com>
12 * MPC83xx PCI-Express support:
20 #include <linux/fsl/edac.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/ppc-pci.h>
39 #include <asm/ppc-opcode.h>
60 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in quirk_fsl_pcie_early()
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