xref: /linux/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml (revision 2f2c7254931f41b5736e3ba12aaa9ac1bbeeeb92) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller
8
9maintainers:
10  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
11
12allOf:
13  - $ref: /schemas/pci/pci-host-bridge.yaml#
14  - $ref: /schemas/pci/snps,dw-pcie.yaml#
15
16properties:
17  compatible:
18    const: amd,versal2-mdb-host
19
20  reg:
21    items:
22      - description: MDB System Level Control and Status Register (SLCR) Base
23      - description: configuration region
24      - description: data bus interface
25      - description: address translation unit register
26
27  reg-names:
28    items:
29      - const: slcr
30      - const: config
31      - const: dbi
32      - const: atu
33
34  ranges:
35    maxItems: 2
36
37  msi-map:
38    maxItems: 1
39
40  interrupts:
41    maxItems: 1
42
43  interrupt-map-mask:
44    items:
45      - const: 0
46      - const: 0
47      - const: 0
48      - const: 7
49
50  interrupt-map:
51    maxItems: 4
52
53  "#interrupt-cells":
54    const: 1
55
56  interrupt-controller:
57    description: identifies the node as an interrupt controller
58    type: object
59    additionalProperties: false
60    properties:
61      interrupt-controller: true
62
63      "#address-cells":
64        const: 0
65
66      "#interrupt-cells":
67        const: 1
68
69    required:
70      - interrupt-controller
71      - "#address-cells"
72      - "#interrupt-cells"
73
74patternProperties:
75  '^pcie@[0-2],0$':
76    type: object
77    $ref: /schemas/pci/pci-pci-bridge.yaml#
78
79    properties:
80      reg:
81        maxItems: 1
82
83    unevaluatedProperties: false
84
85required:
86  - reg
87  - reg-names
88  - interrupts
89  - interrupt-map
90  - interrupt-map-mask
91  - msi-map
92  - "#interrupt-cells"
93  - interrupt-controller
94
95unevaluatedProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    #include <dt-bindings/interrupt-controller/irq.h>
101    #include <dt-bindings/gpio/gpio.h>
102
103    soc {
104        #address-cells = <2>;
105        #size-cells = <2>;
106        pcie@ed931000 {
107            compatible = "amd,versal2-mdb-host";
108            reg = <0x0 0xed931000 0x0 0x2000>,
109                  <0x1000 0x100000 0x0 0xff00000>,
110                  <0x1000 0x0 0x0 0x1000>,
111                  <0x0 0xed860000 0x0 0x2000>;
112            reg-names = "slcr", "config", "dbi", "atu";
113            ranges = <0x2000000 0x00 0xa0000000 0x00 0xa0000000 0x00 0x10000000>,
114                     <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>;
115            interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
116            interrupt-parent = <&gic>;
117            interrupt-map-mask = <0 0 0 7>;
118            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
119                            <0 0 0 2 &pcie_intc_0 1>,
120                            <0 0 0 3 &pcie_intc_0 2>,
121                            <0 0 0 4 &pcie_intc_0 3>;
122            msi-map = <0x0 &gic_its 0x00 0x10000>;
123            #address-cells = <3>;
124            #size-cells = <2>;
125            #interrupt-cells = <1>;
126            device_type = "pci";
127
128            pcie@0,0 {
129                device_type = "pci";
130                reg = <0x0 0x0 0x0 0x0 0x0>;
131                reset-gpios = <&tca6416_u37 7 GPIO_ACTIVE_LOW>;
132                #address-cells = <3>;
133                #size-cells = <2>;
134                ranges;
135            };
136
137            pcie_intc_0: interrupt-controller {
138                #address-cells = <0>;
139                #interrupt-cells = <1>;
140                interrupt-controller;
141            };
142        };
143    };
144