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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dlantiq,pinctrl-xway.txt1 Lantiq XWAY pinmux controller
4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
5 "ase" (XWAY AMAZON Family)
6 "danube" (XWAY DANUBE Family)
7 "xrx100" (XWAY xRX100 Family)
8 "xrx200" (XWAY xRX200 Family)
9 "xrx300" (XWAY xRX300 Family)
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
21 pull-up and open-drain
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/linux/Documentation/devicetree/bindings/mips/lantiq/
H A Dlantiq,ebu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mips/lantiq/lantiq,ebu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq Xway SoC series External Bus Unit (EBU)
10 - John Crispin <john@phrozen.org>
15 - enum:
16 - lantiq,ebu-xway
22 - compatible
23 - reg
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/linux/arch/mips/boot/dts/lantiq/
H A Ddanube.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "lantiq,xway", "lantiq,danube";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "lantiq,biu", "simple-bus";
21 #interrupt-cells = <1>;
22 interrupt-controller;
34 #address-cells = <1>;
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/linux/drivers/pinctrl/
H A Dpinctrl-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
110 /* --------- ase related code --------- */
116 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
118 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
126 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
127 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
128 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
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/linux/drivers/mtd/nand/raw/
H A Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
76 return readb(data->nandaddr + op); in xway_readb()
84 writeb(value, data->nandaddr + op); in xway_writeb()
92 case -1: in xway_select_chip()
95 spin_unlock_irqrestore(&ebu_lock, data->csflags); in xway_select_chip()
98 spin_lock_irqsave(&ebu_lock, data->csflags); in xway_select_chip()
151 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in xway_attach_chip()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
126 include NAND flash controllers with built-in hardware ECC
154 tristate "Marvell EBU NAND controller"
161 - PXA3xx processors (NFCv1)
162 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
163 - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
229 Controller Module with built-in hardware ECC capabilities.
240 with built-in hardware ECC capabilities.
250 processor localbus with User-Programmable Machine support.
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/linux/arch/mips/lantiq/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* register definitions - internal irqs */
32 /* register definitions - external irqs */
45 * irqs generated by devices attached to the EBU need to be acked in
75 return -1; in ltq_eiu_get_irq()
80 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_disable_irq()
98 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_mask_and_ack_irq()
117 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_ack_irq()
133 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; in ltq_enable_irq()
160 if (d->hwirq == ltq_eiu_irq[i]) { in ltq_eiu_settype()
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/linux/arch/mips/lantiq/xway/
H A Dsysctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
5 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
124 #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */
165 do {} while (--retry && (pmu_r32(PMU_PWDSR) & module)); in ltq_pmu_enable()
180 do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module))); in ltq_pmu_disable()
191 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); in cgu_enable()
198 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); in cgu_disable()
208 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module)); in pmu_enable()
209 do {} while (--retry && in pmu_enable()
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