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/linux/drivers/mmc/host/
H A Dsdhci-of-esdhc.c3 * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
71 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
75 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
76 { .compatible = "fsl,mpc8379-esdhc" },
77 { .compatible = "fsl,mpc8536-esdhc" },
78 { .compatible = "fsl,esdhc" },
[all …]
H A Dsdhci-esdhc-mcf.c3 * Freescale eSDHC ColdFire family controller driver, platform bus.
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
14 #include "sdhci-esdhc.h"
21 * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
235 * ColdFire eSDHC clock.s in esdhc_mcf_pltfm_set_clock()
238 * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS in esdhc_mcf_pltfm_set_clock()
241 * (8.1.2) eSDHC should be 40 MHz max in esdhc_mcf_pltfm_set_clock()
242 * (25.3.9) eSDHC input is, as example, 96 Mhz ... in esdhc_mcf_pltfm_set_clock()
511 .name = "sdhci-esdhc-mcf",
520 MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
H A Dsdhci-pltfm.c61 if (device_is_compatible(dev, "fsl,p2020-rev1-esdhc")) in sdhci_get_compatibility()
64 if (device_is_compatible(dev, "fsl,p2020-esdhc") || in sdhci_get_compatibility()
65 device_is_compatible(dev, "fsl,p1010-esdhc") || in sdhci_get_compatibility()
66 device_is_compatible(dev, "fsl,t4240-esdhc") || in sdhci_get_compatibility()
67 device_is_compatible(dev, "fsl,mpc8536-esdhc")) in sdhci_get_compatibility()
H A Dsdhci-esdhc.h3 * Freescale eSDHC controller driver generics for OF and pltfm.
16 * Ops and quirks for the Freescale eSDHC controller.
30 * eSDHC register definition
H A Dsdhci-esdhc-imx.c3 * Freescale eSDHC i.MX controller driver for the platform bus.
30 #include "sdhci-esdhc.h"
127 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
128 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
129 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
130 * Define this macro DMA error INT for fsl eSDHC
150 * The flag tells that the ESDHC controller is an USDHC block that is
221 * struct esdhc_platform_data - platform data for esdhc on i.MX
364 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
365 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
[all …]
H A DMakefile80 obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o
81 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
87 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
H A DKconfig205 tristate "SDHCI OF support for the Freescale eSDHC controller"
211 This selects the Freescale eSDHC controller support.
280 tristate "SDHCI support for the Freescale eSDHC ColdFire controller"
285 This selects the Freescale eSDHC controller support for
293 tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller"
300 This selects the Freescale eSDHC/uSDHC controller support
/linux/Documentation/devicetree/bindings/mmc/
H A Dfsl,esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC)
20 - fsl,mpc8536-esdhc
21 - fsl,mpc8378-esdhc
22 - fsl,p2020-esdhc
23 - fsl,p4080-esdhc
24 - fsl,t1040-esdhc
25 - fsl,t4240-esdhc
26 - fsl,ls1012a-esdhc
27 - fsl,ls1028a-esdhc
[all …]
H A Dfsl-imx-esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
39 - const: fsl,imx50-esdhc
40 - const: fsl,imx53-esdhc
115 because the signal path is too long on the board. Please refer to eSDHC/uSDHC
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50.dtsi119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
H A Dimx35.dtsi235 compatible = "fsl,imx35-esdhc";
244 compatible = "fsl,imx35-esdhc";
253 compatible = "fsl,imx35-esdhc";
/linux/arch/arm64/boot/dts/freescale/
H A Dtqmls10xxa.dtsi49 &esdhc {
50 /* eSDHC or eMMC: set by bootloader */
H A Dfsl-ls1028a-kontron-sl28.dts27 mmc1 = &esdhc;
100 &esdhc {
H A Dfsl-ls1012a.dtsi160 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
178 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
H A Dfsl-ls1046a-tqmls1046a-mbls10xxa.dts42 &esdhc {
/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
36 compatible = "fsl,esdhc";
H A Dqoriq-esdhc-0.dtsi2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
36 compatible = "fsl,esdhc";
H A Dc293si-post.dtsi113 /include/ "pq3-esdhc-0.dtsi"
115 compatible = "fsl,c293-esdhc", "fsl,esdhc";
H A Dp1010si-post.dtsi172 /include/ "pq3-esdhc-0.dtsi"
174 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
H A Dp1020si-post.dtsi154 /include/ "pq3-esdhc-0.dtsi"
156 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
H A Dp2020si-post.dtsi202 /include/ "pq3-esdhc-0.dtsi"
204 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
H A Dp1022si-post.dtsi215 /include/ "pq3-esdhc-0.dtsi"
217 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
H A Dmpc8536si-post.dtsi243 /include/ "pq3-esdhc-0.dtsi"
245 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
H A Dmvme2500.dts270 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
/linux/arch/m68k/coldfire/
H A Dm5441x.c56 DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
118 CLKDEV_INIT("sdhci-esdhc-mcf.0", NULL, &__clk_0_51),
161 &__clk_0_51, /* esdhc */

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