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/linux/Documentation/devicetree/bindings/phy/
H A Dintel,lgm-emmc-phy.yaml4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14 node is used to reference the base address of eMMC phy registers.
16 The eMMC PHY node should be the child of a syscon node with the
27 - intel,lgm-emmc-phy
28 - intel,keembay-emmc-phy
59 emmc_phy: emmc-phy@a8 {
60 compatible = "intel,lgm-emmc-phy";
62 clocks = <&emmc>;
[all …]
H A Drockchip,rk3399-emmc-phy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip,rk3399-emmc-phy.yaml#
7 title: Rockchip EMMC PHY
14 const: rockchip,rk3399-emmc-phy
58 compatible = "rockchip,rk3399-emmc-phy";
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-emmc.yaml4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
7 title: Simple eMMC hardware reset provider
13 The purpose of this driver is to perform standard eMMC hw reset
16 fix possible issues if bootloader has left eMMC card in initialized or
19 doesn't have hardware reset logic connected to emmc card and (limited or
20 broken) ROM bootloaders are unable to read second stage from the emmc
25 const: mmc-pwrseq-emmc
31 and then deasserted to perform eMMC card reset. To perform
45 compatible = "mmc-pwrseq-emmc";
H A Dmarvell,xenon-sdhci.yaml72 PAD is fixed 1.8V, such as for eMMC.
86 - emmc 5.1 phy
87 - emmc 5.0 phy
89 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
90 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
91 choice if this property is not provided. To select eMMC 5.0 PHY, set:
92 marvell,xenon-phy-type = "emmc 5.0 phy"
94 All those types of PHYs can support eMMC, SD and SDIO. Please note that
96 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
97 that this Xenon SDHC only supports eMMC 5.1.
[all …]
H A Dmmc-controller-common.yaml42 Non-removable slot (like eMMC); assume always present.
85 - for eMMC, the maximum supported frequency is 200MHz,
112 line. Not used in combination with eMMC or SDIO.
173 eMMC hardware reset is supported
193 eMMC high-speed DDR mode (1.2V I/O) is supported.
198 eMMC high-speed DDR mode (1.8V I/O) is supported.
203 eMMC high-speed DDR mode (3.3V I/O) is supported.
208 eMMC HS200 mode (1.2V I/O) is supported.
213 eMMC HS200 mode (1.8V I/O) is supported.
218 eMMC HS400 mode (1.2V I/O) is supported.
[all …]
/linux/Documentation/driver-api/mmc/
H A Dmmc-tools.rst16 - Determine the eMMC writeprotect status.
17 - Set the eMMC writeprotect status.
18 - Set the eMMC data sector size to 4KB by disabling emulation.
25 - Enable the eMMC BKOPS feature.
26 - Permanently enable the eMMC H/W Reset feature.
27 - Permanently disable the eMMC H/W Reset feature.
33 - Enable the eMMC cache feature.
34 - Disable the eMMC cache feature.
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b-ec100.dts30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
427 "NAND_D0 (EMMC)", "NAND_D1 (EMMC)",
428 "NAND_D2 (EMMC)", "NAND_D3 (EMMC)",
429 "NAND_D4 (EMMC)", "NAND_D5 (EMMC)",
430 "NAND_D6 (EMMC)", "NAND_D7 (EMMC)",
431 "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
432 "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
433 "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
434 "nWE_S1 NAND_nWE (EMMC)", "", "", "", "SPI_CS",
H A Dmeson8b-odroidc1.dts30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
262 "SDC_D0 (EMMC)", "SDC_D1 (EMMC)",
263 "SDC_D2 (EMMC)", "SDC_D3 (EMMC)",
264 "SDC_D4 (EMMC)", "SDC_D5 (EMMC)",
265 "SDC_D6 (EMMC)", "SDC_D7 (EMMC)",
266 "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)",
267 "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "",
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-olimex-som-evb-emmc.dts3 * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
14 model = "Olimex A20-Olimex-SOM-EVB-eMMC";
15 compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
18 compatible = "mmc-pwrseq-emmc";
30 emmc: emmc@0 { label
H A Dsun7i-a20-olimex-som204-evb-emmc.dts3 * Device Tree Source for A20-SOM204-EVB-eMMC Board
13 model = "Olimex A20-SOM204-EVB-eMMC";
14 compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
17 compatible = "mmc-pwrseq-emmc";
29 emmc: emmc@0 { label
H A Dsun7i-a20-olinuxino-lime-emmc.dts10 model = "Olimex A20-OLinuXino-LIME-eMMC";
11 compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20";
14 compatible = "mmc-pwrseq-emmc";
27 emmc: emmc@0 { label
H A Dsun7i-a20-olinuxino-micro-emmc.dts47 model = "Olimex A20-OLinuXino-MICRO-eMMC";
48 compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20";
51 compatible = "mmc-pwrseq-emmc";
63 emmc: emmc@0 { label
H A Dsun7i-a20-olinuxino-lime2-emmc.dts47 model = "Olimex A20-OLinuXino-LIME2-eMMC";
48 compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20";
51 compatible = "mmc-pwrseq-emmc";
64 emmc: emmc@0 { label
/linux/arch/arm64/boot/dts/mediatek/
H A DMakefile17 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
22 mt7986a-bananapi-bpi-r3-emmc-nand-dtbs := \
24 mt7986a-bananapi-bpi-r3-emmc.dtbo \
26 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nand.dtb
27 mt7986a-bananapi-bpi-r3-emmc-nor-dtbs := \
29 mt7986a-bananapi-bpi-r3-emmc.dtbo \
31 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nor.dtb
47 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo
52 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo
55 mt7988a-bananapi-bpi-r4-emmc-dtbs := \
[all …]
/linux/Documentation/devicetree/bindings/soc/intel/
H A Dintel,lgm-syscon.yaml31 "^emmc-phy@[0-9a-f]+$":
32 $ref: /schemas/phy/intel,lgm-emmc-phy.yaml#
51 emmc-phy@a8 {
52 compatible = "intel,lgm-emmc-phy";
54 clocks = <&emmc>;
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-colibri-emmc-iris.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
13 compatible = "toradex,colibri-imx6ull-emmc-iris",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx6ull-colibri-emmc-eval-v3.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3";
13 compatible = "toradex,colibri-imx6ull-emmc-eval",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx6ull-colibri-emmc-aster.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
13 compatible = "toradex,colibri-imx6ull-emmc-aster",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx6ull-colibri-emmc-iris-v2.dts8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
13 compatible = "toradex,colibri-imx6ull-emmc-iris-v2",
14 "toradex,colibri-imx6ull-emmc",
H A Dimx7d-colibri-emmc-aster.dts8 #include "imx7d-colibri-emmc.dtsi"
12 model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board";
13 compatible = "toradex,colibri-imx7d-emmc-aster",
14 "toradex,colibri-imx7d-emmc",
H A Dimx7d-colibri-emmc-eval-v3.dts7 #include "imx7d-colibri-emmc.dtsi"
11 model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3";
12 compatible = "toradex,colibri-imx7d-emmc-eval-v3",
13 "toradex,colibri-imx7d-emmc",
/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c20 /* Register base for eMMC PHY 5.0 Version */
22 /* Register base for eMMC PHY 5.1 Version */
117 * in eMMC PHY 5.0 or eMMC PHY 5.1
139 "emmc 5.0 phy",
140 "emmc 5.1 phy"
187 * eMMC PHY configuration and operations
236 * eMMC 5.0/5.1 PHY init/re-init.
237 * eMMC PHY init should be executed after:
300 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", in xenon_emmc_phy_init()
346 * Enable eMMC PHY HW DLL
[all …]
/linux/drivers/phy/intel/
H A DKconfig6 tristate "Intel Keem Bay EMMC PHY driver"
15 will be called phy-keembay-emmc.ko.
44 tristate "Intel Lightning Mountain EMMC PHY driver"
48 Enable this to support the Intel EMMC PHY
H A Dphy-intel-lgm-emmc.c3 * Intel eMMC PHY driver
18 /* eMMC phy register definitions */
216 /* Power up eMMC phy analog blocks */ in intel_emmc_phy_power_on()
222 /* Power down eMMC phy analog blocks */ in intel_emmc_phy_power_off()
246 /* Get eMMC phy (accessed via chiptop) regmap */ in intel_emmc_phy_probe()
266 { .compatible = "intel,lgm-emmc-phy" },
275 .name = "intel-emmc-phy",
283 MODULE_DESCRIPTION("Intel eMMC PHY driver");
H A Dphy-intel-keembay-emmc.c3 * Intel Keem Bay eMMC PHY driver
18 /* eMMC/SD/SDIO core/phy configuration registers */
98 /* Check for EMMC clock rate*/ in keembay_emmc_phy_power()
241 /* Power up eMMC phy analog blocks */ in keembay_emmc_phy_power_on()
247 /* Power down eMMC phy analog blocks */ in keembay_emmc_phy_power_off()
292 { .compatible = "intel,keembay-emmc-phy" },
300 .name = "keembay-emmc-phy",
307 MODULE_DESCRIPTION("Intel Keem Bay eMMC PHY driver");

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