dynamically\-programmable (full) in projects: linux

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Searched +full:dynamically +full:- +full:programmable (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/usb/gadget/udc/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0 7 # NOTE: Gadget support DOES NOT depend on host-side CONFIG_USB !! 9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks). 10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks). 11 # - Some systems have both kinds of controllers. 13 # With help from a special transceiver and a "Mini-AB" jack, systems with 14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG). 22 # - integrated/SOC controllers first 23 # - licensed IP used in both SOC and discrete versions 24 # - discrete ones (including all PCI-only controllers) [all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A D	adi,ad5758.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michael Hennerich <Michael.Hennerich@analog.com> 19 spi-cpha: true 21 adi,dc-dc-mode: 25 Mode of operation of the dc-to-dc converter 28 dynamically regulates the supply voltage, VDPC+, to meet compliance 31 Programmable Power Control (PPC) 32 In this mode, the VDPC+ voltage is user-programmable to a fixed level [all …]`
/linux/Documentation/sound/soc/
H A D	pops-clicks.rst	`11 because the components within the subsystem are being dynamically powered 23 shutdown and follows some basic rules:- 26 Startup Order :- DAC --> Mixers --> Output PGA --> Digital Unmute 28 Shutdown Order :- Digital Mute --> Output PGA --> Mixers --> DAC 31 a PGA (programmable gain amplifier) before being output to the speakers. 43 Startup Order - Input PGA --> Mixers --> ADC 45 Shutdown Order - ADC --> Mixers --> Input PGA`
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	pipeline.json	8 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", 128 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 146 "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 150 "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 177 "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", 204 "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 212 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 229 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", 355 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-lin [all...]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	pipeline.json	8 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", 128 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 146 "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 150 "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 177 "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", 204 "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 212 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 229 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", 355 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-lin [all...]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	pipeline.json	8 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 128 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 146 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX … 150 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE… 177 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 204 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread … 212 … event. It is counted on a dedicated fixed counter, leaving the eight programmable counters availa… 229 … state. It is counted on a dedicated fixed counter, leaving the eight programmable counters availa… 374 …dynamically changing prefix length of the decoded instruction (by operand size prefix instruction … 388 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	pipeline.json	8 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 128 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 146 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX … 150 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE… 177 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 204 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread … 212 … event. It is counted on a dedicated fixed counter, leaving the eight programmable counters availa… 229 … state. It is counted on a dedicated fixed counter, leaving the eight programmable counters availa… 355 …dynamically changing prefix length of the decoded instruction (by operand size prefix instruction … 369 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", [all …]
/linux/drivers/pwm/
H A D	pwm-tegra.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * drivers/pwm/pwm-tegra.c 5 * Tegra pulse-width-modulation controller driver 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 16 * on the programmable frequency division value to generate the required 28 * - When PWM is disabled, the output is driven to inactive. [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	pipeline.json	3 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 130 …"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Cou… 187 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 228 …xed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters availa… 263 …xed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters availa… 412 …dynamically changing prefix length of the decoded instruction (by operand size prefix instruction … 429 …-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during har… 434 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 439 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in… 488 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path … [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	pipeline.json	3 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 130 …"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Cou… 187 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 228 …xed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters availa… 263 …xed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters availa… 412 …dynamically changing prefix length of the decoded instruction (by operand size prefix instruction … 429 …-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during har… 434 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 439 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in… 488 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path … [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	pipeline.json	3 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 130 …"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Cou… 218 …xed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters availa… 253 …xed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters availa… 402 …dynamically changing prefix length of the decoded instruction (by operand size prefix instruction … 419 …-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during har… 424 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 429 …n": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions in… 478 …"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path … 535 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F… [all …]
/linux/drivers/mmc/host/
H A D	sdhci-msm.c	`1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver 5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 23 #include "sdhci-cqhci.h" 24 #include "sdhci-pltfm.h" 124 #define INVALID_TUNING_PHASE -1 141 /* Max load for eMMC Vdd-io supply / 147 / Max load for SD Vdd-io supply */ 151 msm_host->var_ops->msm_readl_relaxed(host, offset) 154 msm_host->var_ops->msm_writel_relaxed(val, host, offset) [all …]`
/linux/tools/include/uapi/linux/
H A D	bpf.h	`1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note / 2 / Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com 21 #define BPF_DW 0x18 /* double word (64-bit) / 23 #define BPF_ATOMIC 0xc0 / atomic memory ops - op type in immediate / 24 #define BPF_XADD 0xc0 / exclusive add - legacy name / 32 #define BPF_TO_LE 0x00 / convert to little-endia [all...]`
/linux/drivers/video/fbdev/
H A D	amifb.c	2 * linux/drivers/video/amifb.c -- Amiga builtin chipset frame buffer device 4 * Copyright (C) 1995-2003 Geert Uytterhoeven 30 * - 24 Jul 96: Copper generates now vblank interrupt and 32 * - 14 Jul 96: Rework and hopefully last ECS bugs fixed 33 * - 7 Mar 96: Hardware sprite support by Roman Zippel 34 * - 18 Feb 96: OCS and ECS support by Roman Zippel 36 * - 2 Dec 95: AGA version by Geert Uytterhoeven 107 --------------------- 111 +----------+---------------------------------------------+----------+-------+ 115 +----------###############################################----------+-------+ [all …]
/linux/drivers/net/ethernet/sfc/
H A D	mcdi_pcol.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 4 Copyright 2009-2018 Solarflare Communications Inc. 5 * Copyright 2019-2020 Xilinx Inc. 13 /* Power-on reset state / 35 / The 'doorbell' addresses are hard-wired to alert the MC when written / 38 / The rest of these are firmware-defined / 46 / Values to be written to the per-port status dword in shared 71 * \| \| \--- Response 72 * \| \------- Error 73 * \------------------------------ Resync (always set) [all …]`