1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Altera SOCFPGA SoC DWMAC controller 8 9maintainers: 10 - Maxime Chevallier <maxime.chevallier@bootlin.com> 11 12description: 13 This binding describes the Altera SOCFPGA SoC implementation of the 14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7 15 families of chips. 16 # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that 17 # does not validate against net/snps,dwmac.yaml. 18 19select: 20 properties: 21 compatible: 22 contains: 23 enum: 24 - altr,socfpga-stmmac 25 - altr,socfpga-stmmac-a10-s10 26 - altr,socfpga-stmmac-agilex5 27 28 required: 29 - compatible 30 31properties: 32 compatible: 33 oneOf: 34 - items: 35 - const: altr,socfpga-stmmac 36 - const: snps,dwmac-3.70a 37 - const: snps,dwmac 38 - items: 39 - const: altr,socfpga-stmmac-a10-s10 40 - const: snps,dwmac-3.72a 41 - const: snps,dwmac 42 - items: 43 - const: altr,socfpga-stmmac-a10-s10 44 - const: snps,dwmac-3.74a 45 - const: snps,dwmac 46 - items: 47 - const: altr,socfpga-stmmac-agilex5 48 - const: snps,dwxgmac-2.10 49 50 clocks: 51 minItems: 1 52 items: 53 - description: GMAC main clock 54 - description: 55 PTP reference clock. This clock is used for programming the 56 Timestamp Addend Register. If not passed then the system 57 clock will be used and this is fine on some platforms. 58 59 clock-names: 60 minItems: 1 61 items: 62 - const: stmmaceth 63 - const: ptp_ref 64 65 interrupts: 66 minItems: 1 67 maxItems: 17 68 69 interrupt-names: 70 minItems: 1 71 items: 72 - const: macirq 73 - const: tx-queue-0 74 - const: tx-queue-1 75 - const: tx-queue-2 76 - const: tx-queue-3 77 - const: tx-queue-4 78 - const: tx-queue-5 79 - const: tx-queue-6 80 - const: tx-queue-7 81 - const: rx-queue-0 82 - const: rx-queue-1 83 - const: rx-queue-2 84 - const: rx-queue-3 85 - const: rx-queue-4 86 - const: rx-queue-5 87 - const: rx-queue-6 88 - const: rx-queue-7 89 90 iommus: 91 minItems: 1 92 maxItems: 2 93 94 phy-mode: 95 enum: 96 - gmii 97 - mii 98 - rgmii 99 - rgmii-id 100 - rgmii-rxid 101 - rgmii-txid 102 - sgmii 103 - 1000base-x 104 105 rxc-skew-ps: 106 description: Skew control of RXC pad 107 108 rxd0-skew-ps: 109 description: Skew control of RX data 0 pad 110 111 rxd1-skew-ps: 112 description: Skew control of RX data 1 pad 113 114 rxd2-skew-ps: 115 description: Skew control of RX data 2 pad 116 117 rxd3-skew-ps: 118 description: Skew control of RX data 3 pad 119 120 rxdv-skew-ps: 121 description: Skew control of RX CTL pad 122 123 txc-skew-ps: 124 description: Skew control of TXC pad 125 126 txen-skew-ps: 127 description: Skew control of TXC pad 128 129 altr,emac-splitter: 130 $ref: /schemas/types.yaml#/definitions/phandle 131 description: 132 Should be the phandle to the emac splitter soft IP node if DWMAC 133 controller is connected an emac splitter. 134 135 altr,f2h_ptp_ref_clk: 136 $ref: /schemas/types.yaml#/definitions/phandle 137 description: 138 Phandle to Precision Time Protocol reference clock. This clock is 139 common to gmac instances and defaults to osc1. 140 141 altr,gmii-to-sgmii-converter: 142 $ref: /schemas/types.yaml#/definitions/phandle 143 description: 144 Should be the phandle to the gmii to sgmii converter soft IP. 145 146 altr,sysmgr-syscon: 147 $ref: /schemas/types.yaml#/definitions/phandle-array 148 description: 149 Should be the phandle to the system manager node that encompass 150 the glue register, the register offset, and the register shift. 151 On Cyclone5/Arria5, the register shift represents the PHY mode 152 bits, while on the Arria10/Stratix10/Agilex platforms, the 153 register shift represents bit for each emac to enable/disable 154 signals from the FPGA fabric to the EMAC modules. 155 items: 156 - items: 157 - description: phandle to the system manager node 158 - description: offset of the control register 159 - description: shift within the control register 160 161patternProperties: 162 "^mdio[0-9]$": 163 type: object 164 165required: 166 - compatible 167 - clocks 168 - clock-names 169 - altr,sysmgr-syscon 170 - interrupts 171 - interrupt-names 172 173allOf: 174 - $ref: snps,dwmac.yaml# 175 176 - if: 177 properties: 178 compatible: 179 contains: 180 const: altr,socfpga-stmmac-agilex5 181 then: 182 properties: 183 interrupts: 184 minItems: 17 185 186 interrupt-names: 187 minItems: 17 188 189 dma-coherent: true 190 else: 191 properties: 192 interrupts: 193 maxItems: 1 194 195 interrupt-names: 196 maxItems: 1 197 198 dma-coherent: false 199 200unevaluatedProperties: false 201 202examples: 203 204 - | 205 #include <dt-bindings/interrupt-controller/arm-gic.h> 206 #include <dt-bindings/interrupt-controller/irq.h> 207 soc { 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ethernet@ff700000 { 211 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", 212 "snps,dwmac"; 213 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 214 reg = <0xff700000 0x2000>; 215 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "macirq"; 217 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 218 clocks = <&emac_0_clk>; 219 clock-names = "stmmaceth"; 220 phy-mode = "sgmii"; 221 }; 222 }; 223