/linux/Documentation/devicetree/bindings/usb/ |
H A D | qcom,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 7 title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller 12 # Use the combined qcom,snps-dwc3 instead 19 const: qcom,dwc3 27 - qcom,ipq4019-dwc3 28 - qcom,ipq5018-dwc3 29 - qcom,ipq5332-dwc3 30 - qcom,ipq5424-dwc3 31 - qcom,ipq6018-dwc3 32 - qcom,ipq8064-dwc3 [all …]
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H A D | qcom,snps-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml# 7 title: Qualcomm SuperSpeed DWC3 USB SoC controller 13 Describes the Qualcomm USB block, based on Synopsys DWC3. 19 const: qcom,snps-dwc3 27 - qcom,ipq4019-dwc3 28 - qcom,ipq5018-dwc3 29 - qcom,ipq5332-dwc3 30 - qcom,ipq5424-dwc3 31 - qcom,ipq6018-dwc3 32 - qcom,ipq8064-dwc3 [all …]
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H A D | rockchip,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml# 7 title: Rockchip SuperSpeed DWC3 USB SoC controller 13 The common content of the node is defined in snps,dwc3.yaml. 28 - rockchip,rk3328-dwc3 29 - rockchip,rk3562-dwc3 30 - rockchip,rk3568-dwc3 31 - rockchip,rk3576-dwc3 32 - rockchip,rk3588-dwc3 40 - rockchip,rk3328-dwc3 41 - rockchip,rk3562-dwc3 [all …]
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H A D | realtek,rtd-dwc3.yaml | 5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml# 8 title: Realtek DWC3 USB SoC Controller Glue 14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0 21 - realtek,rtd1295-dwc3 22 - realtek,rtd1315e-dwc3 23 - realtek,rtd1319-dwc3 24 - realtek,rtd1319d-dwc3 25 - realtek,rtd1395-dwc3 26 - realtek,rtd1619-dwc3 27 - realtek,rtd1619b-dwc3 [all …]
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H A D | dwc3-st.txt | 1 ST DWC3 glue logic 3 This file documents the parameters for the dwc3-st driver. 4 This driver controls the glue logic used to configure the dwc3 core on 8 - compatible : must be "st,stih407-dwc3" 32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the 33 example below. The DT binding details of dwc3 can be found in: 34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml 37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host" 44 st_dwc3: dwc3@8f94000 { 45 compatible = "st,stih407-dwc3"; [all …]
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H A D | omap-usb.txt | 46 OMAP DWC3 GLUE 48 * "ti,dwc3" for OMAP5 and DRA7 49 * "ti,am437x-dwc3" for AM437x 60 - extcon : phandle for the extcon device omap dwc3 uses to detect 65 The dwc3 core should be added as subnode to omap dwc3 glue. 66 - dwc3 : 67 The binding details of dwc3 can be found in: 68 Documentation/devicetree/bindings/usb/snps,dwc3.yaml 71 compatible = "ti,dwc3";
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H A D | fsl,ls1028a.yaml | 7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller 17 - fsl,ls1028a-dwc3 25 - fsl,ls1028a-dwc3 26 - const: snps,dwc3 42 - $ref: snps,dwc3.yaml# 49 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
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H A D | fsl,imx8mq-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml# 18 - fsl,imx8mq-dwc3 25 - const: fsl,imx8mq-dwc3 26 - const: snps,dwc3 29 - $ref: snps,dwc3.yaml# 39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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H A D | ti,keystone-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml# 16 - ti,keystone-dwc3 17 - ti,am654-dwc3 61 $ref: snps,dwc3.yaml# 77 dwc3@2680000 { 78 compatible = "ti,keystone-dwc3"; 87 compatible = "snps,dwc3";
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H A D | dwc3-xilinx.yaml | 4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml# 7 title: Xilinx SuperSpeed DWC3 USB SoC controller 16 - xlnx,zynqmp-dwc3 17 - xlnx,versal-dwc3 84 $ref: snps,dwc3.yaml# 114 compatible = "xlnx,zynqmp-dwc3"; 128 compatible = "snps,dwc3";
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H A D | hisilicon,hi3798mv200-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml# 7 title: HiSilicon Hi3798MV200 DWC3 USB SoC controller 14 const: hisilicon,hi3798mv200-dwc3 52 $ref: snps,dwc3.yaml# 71 compatible = "hisilicon,hi3798mv200-dwc3"; 87 compatible = "snps,dwc3";
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H A D | amlogic,meson-g12a-usb-ctrl.yaml | 8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue 14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY. 22 The DWC3 Glue controls the PHY routing and power, an interrupt line is 25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in 84 - $ref: snps,dwc3.yaml# 229 dwc3: usb@ff500000 { 230 compatible = "snps,dwc3";
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H A D | rockchip,rk3399-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml# 7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller 14 const: rockchip,rk3399-dwc3 57 $ref: snps,dwc3.yaml# 82 compatible = "rockchip,rk3399-dwc3"; 96 compatible = "snps,dwc3";
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H A D | dwc3-cavium.txt | 1 Cavium SuperSpeed DWC3 USB SoC controller 7 A child node must exist to represent the core DWC3 IP block. The name of 8 the node is not important. The content of the node is defined in dwc3.txt. 23 compatible = "cavium,octeon-7130-xhci", "snps,dwc3";
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/linux/drivers/usb/dwc3/ |
H A D | dwc3-haps.c | 3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer 20 * @dwc3: child dwc3 platform_device 24 struct platform_device *dwc3; member 60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe() 61 if (!dwc->dwc3) in dwc3_haps_probe() 75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe() 77 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe() 82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe() 84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe() 88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe() [all …]
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H A D | glue.h | 14 * @dwc: Reference to dwc3 context structure 15 * @res: resource for the DWC3 core mmio region 17 * be ignored by the DWC3 core, as they are managed by the glue 20 struct dwc3 *dwc; 26 void dwc3_core_remove(struct dwc3 *dwc); 28 int dwc3_runtime_suspend(struct dwc3 *dwc); 29 int dwc3_runtime_resume(struct dwc3 *dwc); 30 int dwc3_runtime_idle(struct dwc3 *dwc); 31 int dwc3_pm_suspend(struct dwc3 *dwc); 32 int dwc3_pm_resume(struct dwc3 *dwc); [all …]
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H A D | dwc3-imx8mp.c | 3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer 54 struct platform_device *dwc3; member 103 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_wakeup_enable() local 106 if (!dwc3) in dwc3_imx8mp_wakeup_enable() 111 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) { in dwc3_imx8mp_wakeup_enable() 145 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt() 211 "snps,dwc3"); in dwc3_imx8mp_probe() 213 return dev_err_probe(dev, -ENODEV, "failed to find dwc3 core child\n"); in dwc3_imx8mp_probe() 232 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in dwc3_imx8mp_probe() 236 dwc3_imx->dwc3 = of_find_device_by_node(dwc3_np); in dwc3_imx8mp_probe() [all …]
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H A D | dwc3-pci.c | 3 * dwc3-pci.c - PCI Specific glue layer 75 * @dwc3: child dwc3 platform_device 82 struct platform_device *dwc3; member 284 * Make the pdev name predictable (only 1 DWC3 on BYT) in dwc3_pci_quirks() 288 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks() 289 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; in dwc3_pci_quirks() 309 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks() 316 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local 319 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work() 321 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work() [all …]
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H A D | ep0.c | 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, 40 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb() 68 struct dwc3 *dwc; in dwc3_ep0_start_trans() 92 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue() 195 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue() 223 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart() 258 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt() 268 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt() [all …]
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H A D | gadget.h | 18 struct dwc3; 93 * @reason: cancelled reason for the dwc3 request 110 void dwc3_ep0_interrupt(struct dwc3 *dwc, 112 void dwc3_ep0_out_start(struct dwc3 *dwc); 113 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep); 114 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc); 120 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc); 122 int dwc3_gadget_start_config(struct dwc3 *dwc, unsigned int resource_index); 126 * @dep: dwc3 endpoint 147 static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) in dwc3_gadget_dctl_write_safe()
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H A D | dwc3-qcom-legacy.c | 4 * Inspired by dwc3-of-simple.c 76 struct platform_device *dwc3; member 263 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); in dwc3_qcom_interconnect_init() 306 struct dwc3 *dwc; in dwc3_qcom_is_host() 311 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host() 322 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_read_usb2_speed() 501 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq() 519 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk() 711 "snps,dwc3"); in dwc3_qcom_of_register_core() 713 dev_err(dev, "failed to find dwc3 core child\n"); in dwc3_qcom_of_register_core() [all …]
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H A D | host.c | 29 static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc) in dwc3_power_off_all_roothub_ports() 66 struct dwc3 *dwc; in dwc3_xhci_plat_start() 81 static void dwc3_host_fill_xhci_irq_res(struct dwc3 *dwc, in dwc3_host_fill_xhci_irq_res() 96 static int dwc3_host_get_irq(struct dwc3 *dwc) in dwc3_host_get_irq() 127 int dwc3_host_init(struct dwc3 *dwc) in dwc3_host_init() 135 * Some platforms need to power off all Root hub ports immediately after DWC3 set to host in dwc3_host_init() 174 * WORKAROUND: dwc3 revisions <=3.00a have a limitation in dwc3_host_init() 182 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 300A)) in dwc3_host_init() 221 void dwc3_host_exit(struct dwc3 *dwc) in dwc3_host_exit()
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H A D | ulpi.c | 24 static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read) in dwc3_ulpi_busyloop() 53 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_read() 71 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_ulpi_write() 86 int dwc3_ulpi_init(struct dwc3 *dwc) in dwc3_ulpi_init() 98 void dwc3_ulpi_exit(struct dwc3 *dwc) in dwc3_ulpi_exit()
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/linux/Documentation/devicetree/bindings/soc/socionext/ |
H A D | socionext,uniphier-dwc3-glue.yaml | 4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml# 7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer 13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is 14 a sideband logic handling signals to DWC3 host controller inside 21 - socionext,uniphier-pro4-dwc3-glue 22 - socionext,uniphier-pro5-dwc3-glue 23 - socionext,uniphier-pxs2-dwc3-glue 24 - socionext,uniphier-ld20-dwc3-glue 25 - socionext,uniphier-pxs3-dwc3-glue 26 - socionext,uniphier-nx1-dwc3-glue [all …]
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/linux/Documentation/driver-api/usb/ |
H A D | dwc3.rst | 12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant 40 For details about features supported by your version of DWC3, consult 65 The DWC3 driver sits on the *drivers/usb/dwc3/* directory. All files 69 Because of DWC3's configuration flexibility, the driver is a little 78 Like any other HW, DWC3 has its own set of limitations. To avoid 90 512 on HighSpeed, etc), or DWC3 driver must add a Chained TRB pointing 94 Note that as of this writing, this won't be a problem because DWC3 is 98 about DWC3 and *non-working transfers*. 108 DWC3 driver will try its best to cope with more than 255 requests and, 116 Whenever you encounter a problem with DWC3, first and foremost you [all …]
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