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/linux/Documentation/devicetree/bindings/usb/
H A Dapple,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/apple,dwc3.yaml#
7 title: Apple Silicon DWC3 USB controller
13 Apple Silicon SoCs use a Synopsys DesignWare DWC3 based controller for each of
17 - $ref: snps,dwc3-common.yaml#
24 - apple,t6000-dwc3
25 - apple,t6020-dwc3
26 - apple,t8112-dwc3
27 - const: apple,t8103-dwc3
28 - const: apple,t8103-dwc3
32 - description: Core DWC3 region
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H A Drealtek,rtd-dwc3.yaml5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
21 - realtek,rtd1295-dwc3
22 - realtek,rtd1315e-dwc3
23 - realtek,rtd1319-dwc3
24 - realtek,rtd1319d-dwc3
25 - realtek,rtd1395-dwc3
26 - realtek,rtd1619-dwc3
27 - realtek,rtd1619b-dwc3
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H A Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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H A Dfsl,ls1028a.yaml7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
17 - fsl,ls1012a-dwc3
18 - fsl,ls1043a-dwc3
19 - fsl,ls1046a-dwc3
20 - fsl,ls1088a-dwc3
21 - fsl,ls208xa-dwc3
22 - fsl,lx2160a-dwc3
23 - const: fsl,ls1028a-dwc3
24 - const: fsl,ls1028a-dwc3
45 - $ref: snps,dwc3-common.yaml#
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H A Dfsl,imx8mq-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
18 - fsl,imx8mq-dwc3
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
29 - $ref: snps,dwc3.yaml#
39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
H A Dti,keystone-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
61 $ref: snps,dwc3.yaml#
77 dwc3@2680000 {
78 compatible = "ti,keystone-dwc3";
87 compatible = "snps,dwc3";
H A Ddwc3-xilinx.yaml4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
86 $ref: snps,dwc3.yaml#
106 - xlnx,versal-dwc3
136 compatible = "xlnx,zynqmp-dwc3";
150 compatible = "snps,dwc3";
H A Dhisilicon,hi3798mv200-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml#
7 title: HiSilicon Hi3798MV200 DWC3 USB SoC controller
14 const: hisilicon,hi3798mv200-dwc3
52 $ref: snps,dwc3.yaml#
71 compatible = "hisilicon,hi3798mv200-dwc3";
87 compatible = "snps,dwc3";
H A Damlogic,meson-g12a-usb-ctrl.yaml8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
84 - $ref: snps,dwc3.yaml#
229 dwc3: usb@ff500000 {
230 compatible = "snps,dwc3";
H A Drockchip,rk3399-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
14 const: rockchip,rk3399-dwc3
57 $ref: snps,dwc3.yaml#
82 compatible = "rockchip,rk3399-dwc3";
96 compatible = "snps,dwc3";
H A Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
7 A child node must exist to represent the core DWC3 IP block. The name of
8 the node is not important. The content of the node is defined in dwc3.txt.
23 compatible = "cavium,octeon-7130-xhci", "snps,dwc3";
/linux/drivers/usb/dwc3/
H A Ddwc3-haps.c3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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H A Ddwc3-apple.c3 * Apple Silicon DWC3 Glue driver
7 * - dwc3-qcom.c Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 * - dwc3-of-simple.c Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
20 * This platform requires a very specific sequence of operations to bring up dwc3 and its USB3 PHY:
24 * 2) DWC3 has to be brought up but we must not touch the gadget area or start xhci yet.
25 * 3) The PHY bring-up has to be finalized and dwc3's PIPE interface has to be switched to the
33 * 1) DWC3 has to exit host or gadget mode and must no longer touch those registers
34 * 2) The PHY has to switch dwc3's PIPE interface back to the dummy backend
37 * We also can't transition the PHY from one mode to another while dwc3 is up and running (this is
41 * After both the PHY and dwc3 are initialized we will only ever see a single "new device connected"
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H A Ddwc3-imx8mp.c3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
103 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3_pdev); in dwc3_imx8mp_wakeup_enable() local
106 if (!dwc3) in dwc3_imx8mp_wakeup_enable()
111 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) { in dwc3_imx8mp_wakeup_enable()
145 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3_pdev); in dwc3_imx8mp_interrupt()
161 static void dwc3_imx_pre_set_role(struct dwc3 *dwc, enum usb_role role) in dwc3_imx_pre_set_role()
185 struct dwc3 *dwc3; in dwc3_imx8mp_probe() local
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H A Ddwc3-pci.c3 * dwc3-pci.c - PCI Specific glue layer
77 * @dwc3: child dwc3 platform_device
84 struct platform_device *dwc3; member
286 * Make the pdev name predictable (only 1 DWC3 on BYT) in dwc3_pci_quirks()
290 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
291 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; in dwc3_pci_quirks()
311 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
318 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
321 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
323 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
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H A Dgadget.c41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state()
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { in dwc3_gadget_set_link_state()
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) in dwc3_gadget_set_link_state()
142 static void dwc3_ep0_reset_state(struct dwc3 *dwc) in dwc3_ep0_reset_state()
196 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_del_and_unmap_request()
229 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_giveback()
255 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, in dwc3_send_gadget_generic_command()
316 struct dwc3 *dwc = dep->dwc; in dwc3_send_gadget_ep_cmd()
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H A Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
40 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb()
68 struct dwc3 *dwc; in dwc3_ep0_start_trans()
92 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue()
196 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue()
229 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart()
264 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt()
274 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt()
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H A Dcore.h37 * DWC3 Multiport controllers support up to 15 High-Speed PHYs
85 /* DWC3 registers memory space boundaries */
708 struct dwc3 *dwc;
755 struct dwc3 *dwc;
956 * @status: internal dwc3 request status tracking
1007 void (*pre_set_role)(struct dwc3 *dwc, enum usb_role role);
1008 void (*pre_run_stop)(struct dwc3 *dwc, bool is_on);
1012 * struct dwc3 - representation of our controller
1119 * @sysdev_is_parent: true when dwc3 device has a parent driver
1127 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
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H A Ddwc3-of-simple.c3 * dwc3-of-simple.c - OF glue layer for simple integrations
9 * This is a combination of the old dwc3-qcom.c by Ivan T. Ivanov
52 if (of_device_is_compatible(np, "rockchip,rk3399-dwc3")) in dwc3_of_simple_probe()
172 { .compatible = "rockchip,rk3399-dwc3" },
173 { .compatible = "sprd,sc9860-dwc3" },
174 { .compatible = "allwinner,sun50i-h6-dwc3" },
175 { .compatible = "hisilicon,hi3670-dwc3" },
176 { .compatible = "hisilicon,hi3798mv200-dwc3" },
177 { .compatible = "intel,keembay-dwc3" },
187 .name = "dwc3-of-simple",
H A Ddwc3-qcom-legacy.c4 * Inspired by dwc3-of-simple.c
76 struct platform_device *dwc3; member
263 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); in dwc3_qcom_interconnect_init()
306 struct dwc3 *dwc; in dwc3_qcom_is_host()
311 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
322 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_read_usb2_speed()
501 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
519 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
711 "snps,dwc3"); in dwc3_qcom_of_register_core()
713 dev_err(dev, "failed to find dwc3 core child\n"); in dwc3_qcom_of_register_core()
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H A Ddwc3-google.c3 * dwc3-google.c - Google DWC3 Specific Glue Layer
55 struct dwc3 dwc;
204 struct dwc3 *dwc = &google->dwc; in dwc3_google_resume_irq()
446 ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); in dwc3_google_probe()
463 struct dwc3 *dwc = platform_get_drvdata(pdev); in dwc3_google_remove()
530 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_google_pm_suspend()
543 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_google_pm_resume()
556 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_google_complete()
563 struct dwc3 *dw
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H A Ddebugfs.c283 struct dwc3 *dwc = s->private; in dwc3_host_lsp()
313 struct dwc3 *dwc = s->private; in dwc3_gadget_lsp()
327 struct dwc3 *dwc = s->private; in dwc3_lsp_show()
368 struct dwc3 *dwc = s->private; in dwc3_lsp_write()
394 struct dwc3 *dwc = s->private;
433 struct dwc3 *dwc = s->private; in dwc3_mode_write()
467 struct dwc3 *dwc = s->private;
519 struct dwc3 *dwc = s->private; in dwc3_testmode_write()
564 struct dwc3 *dwc = s->private;
607 struct dwc3 *dw
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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-dwc3-glue.yaml4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
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/linux/Documentation/driver-api/usb/
H A Ddwc3.rst12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant
40 For details about features supported by your version of DWC3, consult
65 The DWC3 driver sits on the *drivers/usb/dwc3/* directory. All files
69 Because of DWC3's configuration flexibility, the driver is a little
78 Like any other HW, DWC3 has its own set of limitations. To avoid
90 512 on HighSpeed, etc), or DWC3 driver must add a Chained TRB pointing
94 Note that as of this writing, this won't be a problem because DWC3 is
98 about DWC3 and *non-working transfers*.
108 DWC3 driver will try its best to cope with more than 255 requests and,
116 Whenever you encounter a problem with DWC3, first and foremost you
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/linux/drivers/phy/qualcomm/
H A DKconfig135 PHY which is usually paired with either the ChipIdea or Synopsys DWC3
155 with DWC3 USB core. It handles PHY initialization, clock
179 chips with DWC3 USB core. It supports initializing and cleaning
199 to the V1 variants. The PHY is paired with a Synopsys DWC3 USB
217 is usually paired with either the ChipIdea or Synopsys DWC3 USB
230 tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
236 Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports

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