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/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
12 # Use the combined qcom,snps-dwc3 instead
19 const: qcom,dwc3
21 - compatible
26 - enum:
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H A Dapple,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/apple,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Silicon DWC3 USB controller
10 - Sven Peter <sven@kernel.org>
13 Apple Silicon SoCs use a Synopsys DesignWare DWC3 based controller for each of
14 their Type-C ports.
17 - $ref: snps,dwc3-common.yaml#
22 - items:
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H A Drealtek,rtd-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
11 - Stanley Chang <stanley_chang@realtek.com>
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
15 and USB 3.0 in host or dual-role mode.
20 - enum:
21 - realtek,rtd1295-dwc3
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H A Drockchip,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
13 The common content of the node is defined in snps,dwc3.yaml.
18 Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
20 Type-C PHY
21 Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml
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H A Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
16 See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
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H A Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
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H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
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H A Dfsl,ls1028a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - enum:
17 - fsl,ls1012a-dwc3
18 - fsl,ls1043a-dwc3
19 - fsl,ls1046a-dwc3
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H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
13 Defines the properties of the DWC3 core as being embedded in either an
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
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H A Drockchip,rk3399-dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
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H A Dfsl,imx8mq-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
18 - fsl,imx8mq-dwc3
20 - compatible
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
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H A Dti,keystone-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Quadros <rogerq@kernel.org>
15 - enum:
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
22 '#address-cells':
25 '#size-cells':
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H A Dhisilicon,hi3798mv200-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Hi3798MV200 DWC3 USB SoC controller
10 - Yang Xiwen <forbidden405@foxmail.com>
14 const: hisilicon,hi3798mv200-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description: Controller bus clock
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H A Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
4 - compatible: Should contain "cavium,octeon-7130-usb-uctl"
7 A child node must exist to represent the core DWC3 IP block. The name of
8 the node is not important. The content of the node is defined in dwc3.txt.
13 compatible = "cavium,octeon-7130-usb-uctl";
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
19 refclk-type-ss = "dlmc_ref_clk0";
20 refclk-type-hs = "dlmc_ref_clk0";
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/linux/drivers/usb/dwc3/
H A Ddwc3-imx8mp.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
19 #include "core.h"
45 #define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
46 #define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
47 #define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
49 #define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
50 #define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
66 struct device *dev = dwc3_imx->dev; in imx8mp_configure_glue()
69 if (!dwc3_imx->glue_base) in imx8mp_configure_glue()
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H A Ddwc3-apple.c1 // SPDX-License-Identifier: GPL-2.0
3 * Apple Silicon DWC3 Glue driver
7 * - dwc3-qcom.c Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 * - dwc3-of-simple.c Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
20 * This platform requires a very specific sequence of operations to bring up dwc3 and its USB3 PHY:
24 * 2) DWC3 has to be brought up but we must not touch the gadget area or start xhci yet.
25 * 3) The PHY bring-up has to be finalized and dwc3's PIPE interface has to be switched to the
33 * 1) DWC3 has to exit host or gadget mode and must no longer touch those registers
34 * 2) The PHY has to switch dwc3's PIPE interface back to the dummy backend
37 * We also can't transition the PHY from one mode to another while dwc3 is up and running (this is
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
24 #include <linux/dma-mapping.h>
39 #include "core.h"
45 #include "../host/xhci-ext-caps.h"
50 * dwc3_get_dr_mode - Validates and sets dr_mode
53 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
56 struct device *dev = dwc->dev; in dwc3_get_dr_mode()
59 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()
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H A Ddwc3-qcom-legacy.c1 // SPDX-License-Identifier: GPL-2.0
4 * Inspired by dwc3-of-simple.c
25 #include "core.h"
76 struct platform_device *dwc3; member
122 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
124 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
127 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
129 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
141 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; in dwc3_qcom_vbus_notifier()
153 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; in dwc3_qcom_host_notifier()
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H A Ddwc3-xilinx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
15 #include <linux/dma-mapping.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst()
74 struct device *dev = priv_data->dev; in dwc3_xlnx_set_coherency()
82 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { in dwc3_xlnx_set_coherency()
83 reg = readl(priv_data->regs + coherency_offset); in dwc3_xlnx_set_coherency()
85 writel(reg, priv_data->regs + coherency_offset); in dwc3_xlnx_set_coherency()
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H A Dhost.c1 // SPDX-License-Identifier: GPL-2.0
3 * host.c - DesignWare USB3 DRD Controller Host Glue
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
16 #include "../host/xhci-port.h"
17 #include "../host/xhci-ext-caps.h"
18 #include "../host/xhci-caps.h"
19 #include "../host/xhci-plat.h"
20 #include "core.h"
26 * dwc3_power_off_all_roothub_ports - Power off all Root hub ports
29 static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc) in dwc3_power_off_all_roothub_ports()
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H A Ddwc3-google.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-google.c - Google DWC3 Specific Glue Layer
21 #include "core.h"
55 struct dwc3 dwc;
81 google->num_rsts = 4; in dwc3_google_rst_init()
82 google->rsts[0].id = "non_sticky"; in dwc3_google_rst_init()
83 google->rsts[1].id = "sticky"; in dwc3_google_rst_init()
84 google->rsts[2].id = "drd_bus"; in dwc3_google_rst_init()
85 google->rsts[3].id = "top"; in dwc3_google_rst_init()
87 ret = devm_reset_control_bulk_get_exclusive(google->dev, in dwc3_google_rst_init()
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/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
124 controllers on Qualcomm chips. This driver supports the high-speed
125 PHY which is usually paired with either the ChipIdea or Synopsys DWC3
133 Enable support for the USB high-speed eUSB2 repeater on Qualcomm
143 with DWC3 USB core. It handles PHY initialization, clock
167 chips with DWC3 USB core. It supports initializing and cleaning
174 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
177 Support for the USB high-speed ULPI compliant phy on Qualcomm
185 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-dwc3-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
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/linux/Documentation/driver-api/usb/
H A Ddwc3.rst2 Synopsys DesignWare Core SuperSpeed USB 3.0 Controller
11 The *Synopsys DesignWare Core SuperSpeed USB 3.0 Controller*
12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant
15 1. Peripheral-only configuration
16 2. Host-only configuration
17 3. Dual-Role configuration
40 For details about features supported by your version of DWC3, consult
41 your IP team and/or *Synopsys DesignWare Core SuperSpeed USB 3.0
46 pipe - ep0)
49 4. Scatter-list support
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,ipq806x-usb-phy-hs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-hs
21 "#phy-cells":
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