Searched +full:dw +full:- +full:umctl2 +full:- +full:ddrc (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller10 - Krzysztof Kozlowski <krzk@kernel.org>11 - Michal Simek <michal.simek@amd.com>14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of17 16-bits or 32-bits or 64-bits wide.19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]