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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-g12a-dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 - A Synopsys DesignWare MIPI DSI Host Controller IP
16 - A TOP control block controlling the Clocks & Resets of the IP
19 - $ref: dsi-controller.yaml#
24 - amlogic,meson-g12a-dw-mipi-dsi
[all …]
/linux/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
62 bool "Rockchip specific extensions for Synopsys DW HDMI"
70 bool "Rockchip specific extensions for Synopsys DW HDMI QP"
78 bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
82 for the Synopsys DesignWare dsi driver. If you want to
83 enable MIPI DSI on RK3288 or RK3399 based SoC, you should
87 bool "Rockchip specific extensions for Synopsys DW MIPI DSI2"
92 enable MIPI DSI on RK3576 or RK3588 based SoC, you should
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
9 rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o
10 rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
11 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
12 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
13 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
14 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI_QP) += dw_hdmi_qp-rockchip.o
15 rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
16 rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI2) += dw-mipi-dsi2-rockchip.o
[all …]
H A Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
274 /* dual-channel */
282 /* being a phy for other mipi hosts */
365 return -EINVAL; in max_mbps_to_parameter()
[all …]
H A Ddw-mipi-dsi2-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
12 #include <linux/media-bus-format.h>
88 const struct dsigrf_reg *field = &dsi2->cdata->grf_regs[index]; in grf_field_write()
93 regmap_write(dsi2->grf_regmap, field->offset, in grf_field_write()
94 (val << field->lsb) | (GENMASK(field->msb, field->lsb) << 16)); in grf_field_write()
107 ret = phy_set_mode(dsi2->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi2_phy_power_on()
109 dev_err(dsi2->dev, "Failed to set phy mode: %d\n", ret); in dw_mipi_dsi2_phy_power_on()
113 phy_configure(dsi2->phy, &dsi2->phy_opts); in dw_mipi_dsi2_phy_power_on()
114 phy_power_on(dsi2->phy); in dw_mipi_dsi2_phy_power_on()
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx93-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
10 - Liu Ying <victor.liu@nxp.com>
13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
14 Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
[all …]
H A Dsnps,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MIPI DSI host controller
10 - Philippe CORNU <philippe.cornu@foss.st.com>
13 This document defines device tree properties for the Synopsys DesignWare MIPI
14 DSI host controller. It doesn't constitute a device tree binding specification
15 by itself but is meant to be referenced by platform-specific device tree
23 - $ref: ../dsi-controller.yaml#
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
3 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
4 obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o
5 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
6 obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
8 obj-$(CONFIG_DRM_DW_HDMI_QP) += dw-hdmi-qp.o
10 obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
11 obj-$(CONFIG_DRM_DW_MIPI_DSI2) += dw-mipi-dsi2.o
H A Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
16 #include <linux/media-bus-format.h>
196 #define N_LANES(n) (((n) - 1) & 0x3)
229 #define VPG_DEFS(name, dsi) \ argument
230 ((void __force *)&((*dsi).vpg_defs.name))
232 #define REGISTER(name, mask, dsi) \ argument
233 { #name, VPG_DEFS(name, dsi), mask, dsi }
239 struct dw_mipi_dsi *dsi; member
[all …]
H A Ddw-mipi-dsi2.c1 // SPDX-License-Identifier: GPL-2.0+
6 * This generic Synopsys DesignWare MIPI DSI2 host driver is based on the
7 * Rockchip version from rockchip/dw-mipi-dsi2.c converted to use bridge APIs.
13 #include <linux/media-bus-format.h>
69 #define PHY_LANES(x) FIELD_PREP(GENMASK(5, 4), (x) - 1)
226 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts, in cri_fifos_wait_avail()
229 dev_err(dsi2->dev, "command interface is busy\n"); in cri_fifos_wait_avail()
241 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) in dw_mipi_dsi2_set_vid_mode()
244 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) in dw_mipi_dsi2_set_vid_mode()
247 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) in dw_mipi_dsi2_set_vid_mode()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #define DRIVER_NAME "meson-dw-mipi-dsi"
34 #define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
61 mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
64 0, mipi_dsi->base + MIPI_DSI_TOP_SW_RESET); in meson_dw_mipi_dsi_hw_init()
69 mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL); in meson_dw_mipi_dsi_hw_init()
72 writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD); in meson_dw_mipi_dsi_hw_init()
82 ret = clk_set_rate(mipi_dsi->bit_clk, in dw_mipi_dsi_phy_init()
83 mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate); in dw_mipi_dsi_phy_init()
85 dev_err(mipi_dsi->dev, "Failed to set DSI Bit clock rate %lu (ret %d)\n", in dw_mipi_dsi_phy_init()
[all …]
H A Dmeson_encoder_dsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
40 return drm_bridge_attach(bridge->encoder, encoder_dsi->next_bridge, in meson_encoder_dsi_attach()
41 &encoder_dsi->bridge, flags); in meson_encoder_dsi_attach()
48 struct drm_atomic_state *state = bridge_state->base.state; in meson_encoder_dsi_atomic_enable()
49 struct meson_drm *priv = encoder_dsi->priv; in meson_encoder_dsi_atomic_enable()
54 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); in meson_encoder_dsi_atomic_enable()
62 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); in meson_encoder_dsi_atomic_enable()
68 meson_venc_mipi_dsi_mode_set(priv, &crtc_state->adjusted_mode); in meson_encoder_dsi_atomic_enable()
71 writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); in meson_encoder_dsi_atomic_enable()
74 priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); in meson_encoder_dsi_atomic_enable()
[all …]
/linux/arch/riscv/boot/dts/allwinner/
H A Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
H A Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
/linux/drivers/gpu/drm/stm/
H A Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
28 /* DSI digital registers & bit definitions */
32 /* DSI wrapper registers & bit definitions */
35 #define WCFGR_DSIM BIT(0) /* DSI Mode */
39 #define WCR_DSIEN BIT(3) /* DSI ENable */
63 /* dsi color format coding according to the datasheet */
86 struct dw_mipi_dsi *dsi; member
94 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
96 writel(val, dsi->base + reg); in dsi_write()
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
/linux/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 HiSilicon Limited.
98 struct dw_dsi dsi; member
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
191 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
[all …]
H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
46 #address-cells = <1>;
47 #size-cells = <0>;
49 cpu-map {
62 compatible = "arm,cortex-a15";
65 clock-names = "cpu";
66 operating-points-v2 = <&cpu0_opp_table>;
[all …]
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
[all …]

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