Lines Matching +full:dw +full:- +full:mipi +full:- +full:dsi
1 // SPDX-License-Identifier: GPL-2.0+
6 * This generic Synopsys DesignWare MIPI DSI2 host driver is based on the
7 * Rockchip version from rockchip/dw-mipi-dsi2.c converted to use bridge APIs.
14 #include <linux/media-bus-format.h>
70 #define PHY_LANES(x) FIELD_PREP(GENMASK(5, 4), (x) - 1)
227 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts,
230 dev_err(dsi2->dev, "command interface is busy\n");
242 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
245 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
248 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
251 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
253 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
258 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val);
260 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, VIDEO_MODE);
261 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
265 dev_err(dsi2->dev, "failed to enter video mode\n");
273 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, DATA_STREAM_MODE);
274 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
278 dev_err(dsi2->dev, "failed to enter data stream mode\n");
286 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, COMMAND_MODE);
287 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
291 dev_err(dsi2->dev, "failed to enter data stream mode\n");
296 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, 0x0);
298 regmap_write(dsi2->regmap, DSI2_SOFT_RESET,
314 sys_clk = clk_get_rate(dsi2->sys_clk) / USEC_PER_SEC;
318 regmap_write(dsi2->regmap, DSI2_PHY_CLK_CFG, val);
323 struct drm_display_mode *mode = &dsi2->mode;
324 u64 sys_clk = clk_get_rate(dsi2->sys_clk);
329 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed
333 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_mbps * USEC_PER_SEC, 16);
336 pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
340 regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG,
347 regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG,
353 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops;
357 ret = phy_ops->get_timing(dsi2->plat_data->priv_data,
358 dsi2->lane_mbps, &timing);
360 dev_err(dsi2->dev, "Retrieving phy timings failed\n");
362 regmap_write(dsi2->regmap, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(timing.data_lp2hs));
363 regmap_write(dsi2->regmap, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(timing.data_hs2lp));
368 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops;
372 phy_ops->get_interface(dsi2->plat_data->priv_data, &iface);
389 val |= PHY_LANES(dsi2->lanes);
391 regmap_write(dsi2->regmap, DSI2_PHY_MODE_CFG, val);
397 /* phy configuration 8 - 10 */
406 if (dsi2->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
409 regmap_write(dsi2->regmap, DSI2_DSI_GENERAL_CFG, val);
410 regmap_write(dsi2->regmap, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel));
417 switch (dsi2->format) {
433 regmap_write(dsi2->regmap, DSI2_IPI_COLOR_MAN_CFG, val);
441 vactive = mode->vdisplay;
442 vsa = mode->vsync_end - mode->vsync_start;
443 vfp = mode->vsync_start - mode->vdisplay;
444 vbp = mode->vtotal - mode->vsync_end;
446 regmap_write(dsi2->regmap, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa));
447 regmap_write(dsi2->regmap, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp));
448 regmap_write(dsi2->regmap, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vactive));
449 regmap_write(dsi2->regmap, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp));
454 struct drm_display_mode *mode = &dsi2->mode;
460 val = mode->hdisplay;
462 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val));
470 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
473 hact = mode->hdisplay;
474 hsa = mode->hsync_end - mode->hsync_start;
475 hbp = mode->htotal - mode->hsync_end;
476 hline = mode->htotal;
478 pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
480 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_mbps * USEC_PER_SEC, 16);
484 regmap_write(dsi2->regmap, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time));
488 regmap_write(dsi2->regmap, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time));
492 regmap_write(dsi2->regmap, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time));
496 regmap_write(dsi2->regmap, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time));
509 regmap_write(dsi2->regmap, MANUAL_MODE_CFG, mode);
516 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data;
520 if (device->lanes > dsi2->plat_data->max_data_lanes) {
521 dev_err(dsi2->dev, "the number of data lanes(%u) is too many\n",
522 device->lanes);
523 return -EINVAL;
526 dsi2->lanes = device->lanes;
527 dsi2->channel = device->channel;
528 dsi2->format = device->format;
529 dsi2->mode_flags = device->mode_flags;
531 bridge = devm_drm_of_get_bridge(dsi2->dev, dsi2->dev->of_node, 1, 0);
535 bridge->pre_enable_prev_first = true;
536 dsi2->panel_bridge = bridge;
538 drm_bridge_add(&dsi2->bridge);
540 if (pdata->host_ops && pdata->host_ops->attach) {
541 ret = pdata->host_ops->attach(pdata->priv_data, device);
553 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data;
556 if (pdata->host_ops && pdata->host_ops->detach) {
557 ret = pdata->host_ops->detach(pdata->priv_data, device);
562 drm_bridge_remove(&dsi2->bridge);
564 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
574 regmap_write(dsi2->regmap, DSI2_CRI_TX_HDR, hdr_val | CMD_TX_MODE(lpm));
578 dev_err(dsi2->dev, "failed to write command header\n");
588 const u8 *tx_buf = packet->payload;
589 int len = packet->payload_length, pld_data_bytes = sizeof(u32);
597 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, le32_to_cpu(word));
601 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, le32_to_cpu(word));
603 len -= pld_data_bytes;
608 memcpy(&word, packet->header, sizeof(packet->header));
615 u8 *payload = msg->rx_buf;
616 int i, j, ret, len = msg->rx_len;
621 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS,
625 dev_err(dsi2->dev, "CRI has no available read data\n");
629 regmap_read(dsi2->regmap, DSI2_CRI_RX_HDR, &val);
642 regmap_read(dsi2->regmap, DSI2_CRI_RX_PLD, &val);
654 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
658 regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG,
662 /* create a packet to the DSI protocol */
665 dev_err(dsi2->dev, "failed to create packet: %d\n", ret);
677 if (msg->rx_buf && msg->rx_len) {
681 nb_bytes = msg->rx_len;
704 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data;
707 if (pdata->get_input_bus_fmts)
708 return pdata->get_input_bus_fmts(pdata->priv_data,
729 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data;
732 bridge_state->input_bus_cfg.flags =
735 if (pdata->mode_fixup) {
736 ret = pdata->mode_fixup(pdata->priv_data, &crtc_state->mode,
737 &crtc_state->adjusted_mode);
740 DRM_MODE_ARG(&crtc_state->mode));
741 return -EINVAL;
752 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops;
754 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, 0);
757 * Switch to command mode before panel-bridge post_disable &
759 * Note: panel-bridge disable & panel disable has been called
764 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
766 if (phy_ops->power_off)
767 phy_ops->power_off(dsi2->plat_data->priv_data);
769 clk_disable_unprepare(dsi2->sys_clk);
770 clk_disable_unprepare(dsi2->pclk);
771 pm_runtime_put(dsi2->dev);
776 /* single-dsi, so no other instance to consider */
777 return dsi2->lanes;
783 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops;
784 void *priv_data = dsi2->plat_data->priv_data;
788 clk_prepare_enable(dsi2->pclk);
789 clk_prepare_enable(dsi2->sys_clk);
791 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi2->mode_flags,
792 lanes, dsi2->format, &dsi2->lane_mbps);
796 pm_runtime_get_sync(dsi2->dev);
799 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
804 if (phy_ops->power_on)
805 phy_ops->power_on(dsi2->plat_data->priv_data);
814 regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG, CLK_TYPE_MASK,
815 dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS ? NON_CONTINUOUS_CLK :
818 regmap_write(dsi2->regmap, DSI2_PWR_UP, POWER_UP);
829 /* Power up the dsi ctl into a command mode */
830 dw_mipi_dsi2_mode_set(dsi2, &dsi2->mode);
840 drm_mode_copy(&dsi2->mode, adjusted_mode);
848 /* Switch to video mode for panel-bridge enable & panel enable */
849 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)
861 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data;
864 if (pdata->mode_valid)
865 mode_status = pdata->mode_valid(pdata->priv_data, mode,
866 dsi2->mode_flags,
868 dsi2->format);
880 encoder->encoder_type = DRM_MODE_ENCODER_DSI;
882 /* Attach the panel-bridge to the dsi bridge */
883 return drm_bridge_attach(encoder, dsi2->panel_bridge, bridge,
902 .name = "dsi2-host",
913 struct device *dev = &pdev->dev;
923 dsi2->dev = dev;
924 dsi2->plat_data = plat_data;
926 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||
927 !plat_data->phy_ops->get_timing)
928 return dev_err_ptr_probe(dev, -ENODEV, "Phy not properly configured\n");
930 if (!plat_data->regmap) {
936 dsi2->regmap = devm_regmap_init_mmio(dev, base,
938 if (IS_ERR(dsi2->regmap))
939 return dev_err_cast_probe(dev, dsi2->regmap, "failed to init regmap\n");
941 dsi2->regmap = plat_data->regmap;
944 dsi2->pclk = devm_clk_get(dev, "pclk");
945 if (IS_ERR(dsi2->pclk))
946 return dev_err_cast_probe(dev, dsi2->pclk, "Unable to get pclk\n");
948 dsi2->sys_clk = devm_clk_get(dev, "sys");
949 if (IS_ERR(dsi2->sys_clk))
950 return dev_err_cast_probe(dev, dsi2->sys_clk, "Unable to get sys_clk\n");
961 ret = clk_prepare_enable(dsi2->pclk);
971 clk_disable_unprepare(dsi2->pclk);
976 dsi2->dsi_host.ops = &dw_mipi_dsi2_host_ops;
977 dsi2->dsi_host.dev = dev;
978 ret = mipi_dsi_host_register(&dsi2->dsi_host);
980 dev_err(dev, "Failed to register MIPI host: %d\n", ret);
985 dsi2->bridge.driver_private = dsi2;
986 dsi2->bridge.of_node = pdev->dev.of_node;
993 mipi_dsi_host_unregister(&dsi2->dsi_host);
1019 return drm_bridge_attach(encoder, &dsi2->bridge, NULL, 0);
1028 MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
1030 MODULE_DESCRIPTION("DW MIPI DSI2 host controller driver");
1032 MODULE_ALIAS("platform:dw-mipi-dsi2");