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Searched +full:dual +full:- +full:lvds +full:- +full:odd +full:- +full:pixels (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/display/bridge/
H A Dthine,thc63lvd1024.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Thine Electronics THC63LVD1024 LVDS Decoder
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
15 streams to parallel data outputs. The chip supports single/dual input/output
16 modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
19 Single or dual operation mode, output data mapping and DDR output modes are
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H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
23 LDB split mode to support a dual link LVDS display. The channel indexes
24 have to be different. Channel0 outputs odd pixels and channel1 outputs
25 even pixels.
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774c0-ek874-idk-2121wr.dts1 // SPDX-License-Identifier: GPL-2.0
4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
9 #include "r8a774c0-ek874.dts"
13 compatible = "pwm-backlight";
16 brightness-levels = <0 4 8 16 32 64 128 255>;
17 default-brightness-level = <6>;
19 power-supply = <&reg_12p0v>;
20 enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
23 panel-lvds {
24 compatible = "advantech,idk-2121wr", "panel-lvds";
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-evk-mx8-dlvds-lcd1.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 panel-lvds {
13 power-supply = <&reg_vext_3v3>;
15 panel-timing {
16 clock-frequency = <148500000>;
19 hfront-porch = <130>;
20 hback-porch = <70>;
21 hsync-len = <30>;
22 vfront-porch = <5>;
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H A Dimx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
11 #include <dt-bindings/clock/imx8mp-clock.h>
14 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
26 #address-cells = <1>;
27 #size-cells = <0>;
31 dual-lvds-odd-pixels;
34 remote-endpoint = <&ldb_lvds_ch0>;
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H A Dimx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
9 #include "imx8mp-pinfunc.h"
11 /dts-v1/;
15 model = "GOcontroll Moduline Display with BOE av123z7m-n17 display";
18 compatible = "boe,av123z7m-n17";
19 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
20 pinctrl-0 = <&pinctrl_panel>;
21 pinctrl-names = "default";
22 power-supply = <&reg_3v3_per>;
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/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9211.c1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
107 return drm_bridge_attach(encoder, ctx->panel_bridge, in lt9211_attach()
108 &ctx->bridge, flags); in lt9211_attach()
117 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid()
119 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid()
125 dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n", in lt9211_read_chipid()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
147 return (crtc_state->active_planes & in is_hdr_mode()
183 return crtc_state->master_transcoder != INVALID_TRANSCODER; in is_trans_port_sync_slave()
189 return crtc_state->sync_mode_slaves_mask != 0; in is_trans_port_sync_master()
201 return ffs(crtc_state->joiner_pipes) - 1; in joiner_primary_pipe()
210 return hweight8(crtc_state->joiner_pipes) >= 2; in is_bigjoiner()
218 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state)); in bigjoiner_primary_pipes()
226 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state)); in bigjoiner_secondary_pipes()
231 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crtc_is_bigjoiner_primary()
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