Lines Matching +full:dual +full:- +full:lvds +full:- +full:odd +full:- +full:pixels
1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
107 return drm_bridge_attach(encoder, ctx->panel_bridge,
108 &ctx->bridge, flags);
117 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3);
119 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret);
126 dev_err(ctx->dev, "Unknown Chip ID: 0x%02x 0x%02x 0x%02x\n",
128 return -EINVAL;
149 return regmap_multi_reg_write(ctx->regmap, lt9211_system_init_seq,
174 /* 0x8588: BIT 6 set = MIPI-RX, BIT 4 unset = LVDS-TX */
177 { REG_DSI_LANE, REG_DSI_LANE_COUNT(ctx->dsi->lanes) },
193 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_phy_seq,
198 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_cal_reset_seq,
203 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_dig_seq,
208 ret = regmap_multi_reg_write(ctx->regmap, lt9211_rx_div_reset_seq,
215 return regmap_multi_reg_write(ctx->regmap, lt9211_rx_div_clear_seq,
230 ret = regmap_write(ctx->regmap, 0x8600, 0x01);
238 ret = regmap_bulk_read(ctx->regmap, 0x8608, bc, sizeof(bc));
245 /* Width/Height/Format Auto-detection */
246 ret = regmap_bulk_read(ctx->regmap, 0xd082, buf, sizeof(buf));
259 dev_err(ctx->dev, "Unsupported DSI pixel format 0x%01x\n",
261 return -EINVAL;
264 if (width != mode->hdisplay) {
265 dev_err(ctx->dev,
267 width, mode->hdisplay);
268 return -EINVAL;
271 if (height != mode->vdisplay) {
272 dev_err(ctx->dev,
274 height, mode->vdisplay);
275 return -EINVAL;
278 dev_dbg(ctx->dev, "RX: %dx%d format=0x%01x byteclock=%d kHz\n",
288 { 0xd00d, (mode->vtotal >> 8) & 0xff },
289 { 0xd00e, mode->vtotal & 0xff },
290 { 0xd00f, (mode->vdisplay >> 8) & 0xff },
291 { 0xd010, mode->vdisplay & 0xff },
292 { 0xd011, (mode->htotal >> 8) & 0xff },
293 { 0xd012, mode->htotal & 0xff },
294 { 0xd013, (mode->hdisplay >> 8) & 0xff },
295 { 0xd014, mode->hdisplay & 0xff },
296 { 0xd015, (mode->vsync_end - mode->vsync_start) & 0xff },
297 { 0xd016, (mode->hsync_end - mode->hsync_start) & 0xff },
298 { 0xd017, ((mode->vsync_start - mode->vdisplay) >> 8) & 0xff },
299 { 0xd018, (mode->vsync_start - mode->vdisplay) & 0xff },
300 { 0xd019, ((mode->hsync_start - mode->hdisplay) >> 8) & 0xff },
301 { 0xd01a, (mode->hsync_start - mode->hdisplay) & 0xff },
304 return regmap_multi_reg_write(ctx->regmap, lt9211_timing,
332 ret = regmap_write(ctx->regmap, 0x822d, 0x48);
336 if (mode->clock < 44000) {
337 ret = regmap_write(ctx->regmap, 0x8235, 0x83);
338 } else if (mode->clock < 88000) {
339 ret = regmap_write(ctx->regmap, 0x8235, 0x82);
340 } else if (mode->clock < 176000) {
341 ret = regmap_write(ctx->regmap, 0x8235, 0x81);
343 dev_err(ctx->dev,
345 mode->clock);
346 return -EINVAL;
355 ret = regmap_multi_reg_write(ctx->regmap, lt9211_pcr_seq,
361 ret = regmap_read_poll_timeout(ctx->regmap, 0xd087, pval, pval & 0x8,
364 dev_err(ctx->dev, "PCR unstable, ret=%i\n", ret);
375 /* BIT(7) is LVDS dual-port */
376 { 0x823b, 0x38 | (ctx->lvds_dual_link ? BIT(7) : 0) },
390 /* LVDS channel order, Odd:Even 0x10..A:B, 0x40..B:A */
391 { 0x8646, ctx->lvds_dual_link_even_odd_swap ? 0x40 : 0x10 },
401 { 0x855c, ctx->lvds_dual_link ? BIT(0) : 0 },
414 { 0x8237, ctx->lvds_dual_link ? 0x2a : 0x29 },
426 ret = regmap_multi_reg_write(ctx->regmap, system_lt9211_tx_phy_seq,
431 ret = regmap_multi_reg_write(ctx->regmap, system_lt9211_tx_dig_seq,
436 ret = regmap_multi_reg_write(ctx->regmap, system_lt9211_tx_pll_seq,
441 ret = regmap_read_poll_timeout(ctx->regmap, 0x871f, pval, pval & 0x80,
444 dev_err(ctx->dev, "TX PLL unstable, ret=%i\n", ret);
448 ret = regmap_read_poll_timeout(ctx->regmap, 0x8720, pval, pval & 0x80,
451 dev_err(ctx->dev, "TX PLL unstable, ret=%i\n", ret);
472 ret = regulator_enable(ctx->vccio);
474 dev_err(ctx->dev, "Failed to enable vccio: %d\n", ret);
479 gpiod_set_value(ctx->reset_gpio, 1);
480 usleep_range(20000, 21000); /* Very long post-reset delay. */
482 /* Get the LVDS format from the bridge state. */
484 bus_flags = bridge_state->output_bus_cfg.flags;
486 switch (bridge_state->output_bus_cfg.format) {
502 * LVDS bus pixel format, use SPWG24 default
507 dev_warn(ctx->dev,
508 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
509 bridge_state->output_bus_cfg.format);
518 bridge->encoder);
519 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
521 mode = &crtc_state->adjusted_mode;
552 dev_dbg(ctx->dev, "LT9211 enabled.\n");
565 gpiod_set_value(ctx->reset_gpio, 0);
568 ret = regulator_disable(ctx->vccio);
570 dev_err(ctx->dev, "Failed to disable vccio: %d\n", ret);
572 regcache_mark_dirty(ctx->regmap);
580 /* LVDS output clock range 25..176 MHz */
581 if (mode->clock < 25000)
583 if (mode->clock > 176000)
608 /* This is the DSI-end bus format */
630 struct device *dev = ctx->dev;
635 ctx->vccio = devm_regulator_get(dev, "vccio");
636 if (IS_ERR(ctx->vccio))
637 return dev_err_probe(dev, PTR_ERR(ctx->vccio),
640 ctx->lvds_dual_link = false;
641 ctx->lvds_dual_link_even_odd_swap = false;
643 port2 = of_graph_get_port_by_id(dev->of_node, 2);
644 port3 = of_graph_get_port_by_id(dev->of_node, 3);
650 ctx->lvds_dual_link = true;
651 /* Odd pixels to LVDS Channel A, even pixels to B */
652 ctx->lvds_dual_link_even_odd_swap = false;
654 ctx->lvds_dual_link = true;
655 /* Even pixels to LVDS Channel A, odd pixels to B */
656 ctx->lvds_dual_link_even_odd_swap = true;
659 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, &panel_bridge);
668 ctx->panel_bridge = panel_bridge;
680 struct device *dev = ctx->dev;
688 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
696 return -EPROBE_DEFER;
706 ctx->dsi = dsi;
708 dsi->lanes = dsi_lanes;
709 dsi->format = MIPI_DSI_FMT_RGB888;
710 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
726 struct device *dev = &client->dev;
732 return -ENOMEM;
734 ctx->dev = dev;
740 ctx->reset_gpio = devm_gpiod_get_optional(ctx->dev, "reset",
742 if (IS_ERR(ctx->reset_gpio))
743 return PTR_ERR(ctx->reset_gpio);
751 ctx->regmap = devm_regmap_init_i2c(client, <9211_regmap_config);
752 if (IS_ERR(ctx->regmap))
753 return PTR_ERR(ctx->regmap);
758 ctx->bridge.funcs = <9211_funcs;
759 ctx->bridge.of_node = dev->of_node;
760 drm_bridge_add(&ctx->bridge);
764 drm_bridge_remove(&ctx->bridge);
773 drm_bridge_remove(&ctx->bridge);
800 MODULE_DESCRIPTION("Lontium LT9211 DSI/LVDS/DPI bridge driver");