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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
26 - toshiba,tc358775
32 vdd-supply:
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H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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/linux/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
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/linux/include/linux/phy/
H A Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
16 * data lanes, starting from lane 0,
20 * phy to support dual link transmission,
/linux/drivers/soundwire/
H A Dgeneric_bandwidth_allocation.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
21 unsigned int lane; member
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
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/linux/include/linux/
H A Dthunderbolt.h1 /* SPDX-License-Identifier: GPL-2.0 */
46 * enum tb_security_level - Thunderbolt security level
67 * struct tb - main thunderbolt bus structure
103 return (link - 1) / TB_LINKS_PER_PHY_PORT; in tb_phy_port_from_link()
107 * struct tb_property_dir - XDomain property directory
129 * struct tb_property - XDomain property
181 * enum tb_link_width - Thunderbolt/USB4 link width
182 * @TB_LINK_WIDTH_SINGLE: Single lane lin
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H A Dntb.h2 * This file is provided under a dual BSD/GPLv2 license. When using or
8 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
22 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
69 * enum ntb_topo - NTB connection topology
79 NTB_TOPO_NONE = -1,
113 * enum ntb_speed - NTB link training speed
122 NTB_SPEED_AUTO = -1,
131 * enum ntb_width - NTB link training width
134 * @NTB_WIDTH_1: Link is trained to 1 lane width.
135 * @NTB_WIDTH_2: Link is trained to 2 lane width.
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/linux/drivers/ufs/host/
H A Dtc-dwc-g210.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
15 #include "ufshcd-dwc.h"
16 #include "ufshci-dwc.h"
17 #include "tc-dwc-g210.h"
20 * tc_dwc_g210_setup_40bit_rmmi() - configure 40-bit RMMI.
23 * Return: 0 on success or non-zero value on failure.
83 * tc_dwc_g210_setup_20bit_rmmi_lane0() - configure 20-bit RMMI Lane 0.
86 * Return: 0 on success or non-zero value on failure.
135 * tc_dwc_g210_setup_20bit_rmmi_lane1() - configure 20-bit RMMI Lane 1.
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/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
179 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
180 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
242 uint8_t lane0:2; /* Mapping for lane 0 */
243 uint8_t lane1:2; /* Mapping for lane 1 */
244 uint8_t lane2:2; /* Mapping for lane 2 */
245 uint8_t lane3:2; /* Mapping for lane 3 */
263 /* Secondary transmitter configuration for Dual-link DVI */
425 * DFS-bypass flag
433 INVALID_BACKLIGHT = -1
/linux/Documentation/devicetree/bindings/phy/
H A Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy-mipi-dphy.h>
64 "dphy-ref",
65 "dphy-cfg",
110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
162 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
164 unsigned int val = (value << reg->shift) | in rk_dphy_write_grf()
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-usb10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
33 Contact: linux-usb@vger.kernel.org
67 What: /sys/bus/usb-serial/drivers/.../new_id
69 Contact: linux-usb@vger.kernel.org
72 extra bus folder "usb-serial" in sysfs; apart from that
97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
113 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
141 attribute allows user-space to know whether the device is
145 an on-screen keyboard if the only wireless keyboard is
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/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
168 /* PMA TX Lane registers */
189 /* PMA RX Lane registers */
232 /* PHY PCS lane registers */
243 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
244 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
245 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
156 // Bit0:{=0:single, =1:dual},
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
146 /* Bit0:{=0:single, =1:dual},
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/soc/rockchip,vop2.h>
15 #include <dt-bindings/usb/pd.h>
16 #include "rk3588-friendlyelec-cm3588.dtsi"
20 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
22 adc_key_recovery: adc-key-recovery {
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H A Drk3588-firefly-itx-3588j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include "dt-bindings/usb/pd.h"
13 #include "rk3588-firefly-core-3588j.dtsi"
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H A Drk3588s-indiedroid-nova.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
9 #include <dt-bindings/usb/pd.h>
16 adc-keys-0 {
17 compatible = "adc-keys";
18 io-channel-names = "buttons";
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/linux/arch/mips/ath25/
H A Dar5312_regs.h64 #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
65 #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
173 #define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
177 * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
188 #define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
215 * ARM SDRAM Controller -- just enough to determine memory size
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 enc110->base.ctx
59 enc110->base.ctx->logger
62 (enc110->link_regs->reg)
65 (enc110->aux_regs->reg)
68 (enc110->hpd_regs->reg)
75 * ASIC-dependent, actual values for register programming
91 (reg + enc110->offsets.dig)
94 (reg + enc110->offsets.dp)
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
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/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
23 - e GRBG 0
24 - e RGGB 1
25 - e BGGR 2
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-tqma8mpql-mba8mpxl.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "imx8mp-tqma8mpql.dtsi"
16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
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/linux/drivers/net/phy/mscc/
H A Dmscc_serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 * License: Dual MIT/GPL
25 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_detune()
39 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_tune()
56 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_pll_cfg_wr()
85 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_common_cfg_wr()
109 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_des_cfg_wr()
134 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg0_wr()
158 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg1_wr()
180 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg2_wr()
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
28 #include "phy-qcom-qmp-dp-com-v3.h"
51 * for cases when second lane needs different values
70 /* set of registers with offsets different per-PHY */
489 /* struct qmp_phy_cfg - per-PHY initialization config */
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