/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge 10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com> 11 - Sylvain Petinot <sylvain.petinot@foss.st.com> 14 MIPID02 has two CSI-2 input ports, only one of those ports can be 15 active at a time. Active port input stream will be de-serialized 17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 [all …]
|
/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | toshiba,tc358775.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vinay Simha BN <simhavcs@gmail.com> 15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane. 17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel 19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display 25 - toshiba,tc358765 26 - toshiba,tc358775 32 vdd-supply: [all …]
|
H A D | ti,sn65dsi83.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marek Vasut <marex@denx.de> 13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI 14 to 1x Single-link LVDS 16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI 17 to 1x Dual-link or 2x Single-link LVDS 23 - ti,sn65dsi83 24 - ti,sn65dsi84 [all …]
|
/linux/include/linux/phy/ |
H A D | phy-lvds.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 10 * struct phy_configure_opts_lvds - LVDS configuration set 11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential 16 * data lanes, starting from lane 0, 20 * phy to support dual link transmission,
|
/linux/drivers/gpu/drm/bridge/ |
H A D | tc358775.c | 1 // SPDX-License-Identifier: GPL-2.0 16 #include <linux/media-bus-format.h> 36 /* DSI D-PHY Layer Registers */ 37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */ 38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */ 39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */ 40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */ 41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */ 42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */ 44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */ [all …]
|
H A D | tc358762.c | 1 // SPDX-License-Identifier: GPL-2.0 35 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ 36 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ 40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ 41 #define DSI_LANEENABLE 0x0210 /* Enables each lane */ 66 /* Lane enable PPI and DSI register bits */ 84 int ret = ctx->error; in tc358762_clear_error() 86 ctx->error = 0; in tc358762_clear_error() 92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write() 96 if (ctx->error) in tc358762_write() [all …]
|
/linux/drivers/gpu/drm/i915/display/ |
H A D | icl_dsi.c | 75 drm_err(display->drm, "DSI header credits not released\n"); in wait_for_header_credits() 87 drm_err(display->drm, "DSI payload credits not released\n"); in wait_for_payload_credits() 112 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel() 119 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel() 120 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel() 121 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel() 122 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel() 125 drm_err(display->drm, in wait_for_cmds_dispatched_to_panel() 130 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel() 136 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel() [all …]
|
H A D | intel_dpio_phy.c | 2 * Copyright © 2014-2016 Intel Corporation 46 * IOSF-SB port. 49 * houses a common lane part which contains the PLL and other common 50 * logic. CH0 common lane also contains the IOSF-SB logic for the 60 * each spline is made up of one Physical Access Coding Sub-Layer 65 * Additionally the PHY also contains an AUX lane with AUX blocks 71 * Generally on VLV/CHV the common lane corresponds to the pipe and 74 * For dual channel PHY (VLV/CHV): 103 * Dual channel PHY (VLV/CHV/BXT) 104 * --------------------------------- [all …]
|
/linux/drivers/gpu/drm/ |
H A D | drm_of.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 #include <linux/media-bus-format.h> 25 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node 39 if (tmp->port == port) in drm_of_crtc_port_mask() 50 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port 83 * drm_of_component_match_add - Add a component helper OF node match rule 101 * drm_of_component_probe - Generic probe function for a component based master 121 if (!dev->of_node) in drm_of_component_probe() 122 return -EINVAL; in drm_of_component_probe() 129 port = of_parse_phandle(dev->of_node, "ports", i); in drm_of_component_probe() [all …]
|
/linux/include/linux/ |
H A D | thunderbolt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 39 * enum tb_security_level - Thunderbolt security level 60 * struct tb - main thunderbolt bus structure 96 return (link - 1) / TB_LINKS_PER_PHY_PORT; in tb_phy_port_from_link() 100 * struct tb_property_dir - XDomain property directory 122 * struct tb_property - XDomain property 174 * enum tb_link_width - Thunderbolt/USB4 link width 175 * @TB_LINK_WIDTH_SINGLE: Single lane lin [all...] |
/linux/drivers/ufs/host/ |
H A D | tc-dwc-g210.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 15 #include "ufshcd-dwc.h" 16 #include "ufshci-dwc.h" 17 #include "tc-dwc-g210.h" 20 * tc_dwc_g210_setup_40bit_rmmi() - configure 40-bit RMMI. 23 * Return: 0 on success or non-zero value on failure. 83 * tc_dwc_g210_setup_20bit_rmmi_lane0() - configure 20-bit RMMI Lane 0. 86 * Return: 0 on success or non-zero value on failure. 135 * tc_dwc_g210_setup_20bit_rmmi_lane1() - configure 20-bit RMMI Lane 1. [all …]
|
/linux/drivers/thunderbolt/ |
H A D | clx.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2020 - 2023, Intel Corporation 16 MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)"); 44 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set() 54 port->cap_phy + LANE_ADP_CS_1, 1); in tb_port_pm_secondary_set() 73 /* Don't enable CLx in case of two single-lane links */ in tb_port_clx_supported() 74 if (!port->bonded && port->dual_link_port) in tb_port_clx_supported() 77 /* Don't enable CLx in case of inter-domain link */ in tb_port_clx_supported() 78 if (port->xdomain) in tb_port_clx_supported() 81 if (tb_switch_is_usb4(port->sw)) { in tb_port_clx_supported() [all …]
|
H A D | switch.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Thunderbolt driver - switch/port utility functions 12 #include <linux/nvmem-provider.h> 42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status() 57 *status = st ? st->status : 0; in nvm_get_auth_status() 64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status() 75 memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); in nvm_set_auth_status() 76 INIT_LIST_HEAD(&st->list); in nvm_set_auth_status() 77 list_add_tail(&st->list, &nvm_auth_status_cache); in nvm_set_auth_status() 80 st->status = status; in nvm_set_auth_status() [all …]
|
/linux/drivers/gpu/drm/amd/display/include/ |
H A D | grph_object_ctrl_defs.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 179 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */ 180 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */ 242 uint8_t lane0:2; /* Mapping for lane 0 */ 243 uint8_t lane1:2; /* Mapping for lane 1 */ 244 uint8_t lane2:2; /* Mapping for lane 2 */ 245 uint8_t lane3:2; /* Mapping for lane 3 */ 263 /* Secondary transmitter configuration for Dual-link DVI */ 425 * DFS-bypass flag 433 INVALID_BACKLIGHT = -1
|
/linux/Documentation/devicetree/bindings/phy/ |
H A D | intel,combo-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dilip Kota <eswara.kota@linux.intel.com> 18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$" 22 - const: intel,combophy-lgm 23 - const: intel,combo-phy 30 - description: ComboPhy core registers 31 - description: PCIe app core control registers [all …]
|
/linux/drivers/gpu/drm/bridge/synopsys/ |
H A D | dw-mipi-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0+ 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 16 #include <linux/media-bus-format.h> 196 #define N_LANES(n) (((n) - 1) & 0x3) 252 unsigned int lane_mbps; /* per lane */ 268 struct dw_mipi_dsi *master; /* dual-dsi master ptr */ 269 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ 280 return dsi->slave || dsi->master; in dw_mipi_is_dual_mode() 308 writel(val, dsi->base + reg); in dsi_write() 313 return readl(dsi->base + reg); in dsi_read() [all …]
|
/linux/drivers/phy/rockchip/ |
H A D | phy-rockchip-dphy-rx0.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 11 * chromeos-4.4 branch. 14 * Jacob Chen <jacob2.chen@rock-chips.com> 15 * Shunqian Zheng <zhengsq@rock-chips.com> 25 #include <linux/phy/phy-mipi-dphy.h> 64 "dphy-ref", 65 "dphy-cfg", 110 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } 162 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf() 164 unsigned int val = (value << reg->shift) | in rk_dphy_write_grf() [all …]
|
/linux/Documentation/ABI/testing/ |
H A D | sysfs-bus-usb | 10 This allows to avoid side-effects with drivers 28 drivers, non-authorized one are not. By default, wired 33 Contact: linux-usb@vger.kernel.org 67 What: /sys/bus/usb-serial/drivers/.../new_id 69 Contact: linux-usb@vger.kernel.org 72 extra bus folder "usb-serial" in sysfs; apart from that 97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged 113 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged 141 attribute allows user-space to know whether the device is 145 an on-screen keyboard if the only wireless keyboard is [all …]
|
/linux/drivers/gpu/drm/stm/ |
H A D | lvds.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved 4 * Author(s): Raphaël GALLAIS-POU <raphael.gallais-pou@foss.st.com> for STMicroelectronics. 16 #include <linux/clk-provider.h> 19 #include <linux/media-bus-format.h> 62 #define CR_LK1POL GENMASK(20, 16) /* Link-1 output Polarity */ 63 #define CR_LK2POL GENMASK(25, 21) /* Link-2 output Polarity */ 73 #define CDLCR_DISTR0 GENMASK(3, 0) /* Channel distribution for lane 0 */ 74 #define CDLCR_DISTR1 GENMASK(7, 4) /* Channel distribution for lane 1 */ 75 #define CDLCR_DISTR2 GENMASK(11, 8) /* Channel distribution for lane 2 */ [all …]
|
/linux/drivers/gpu/drm/display/ |
H A D | drm_dp_helper.c | 77 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status() 81 int lane) in dp_get_lane_status() argument 83 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status() 84 int s = (lane & 1) * 4; in dp_get_lane_status() 95 int lane; in drm_dp_channel_eq_ok() local 101 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok() 102 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok() 113 int lane; in drm_dp_clock_recovery_ok() local 116 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok() 117 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok() [all …]
|
/linux/arch/arm/boot/dts/nxp/lpc/ |
H A D | lpc4350-hitex-eval.dts | 6 * This code is released using a dual license strategy: BSD/GPL 9 * Released under the terms of 3-clause BSD License 13 /dts-v1/; 18 #include "dt-bindings/input/input.h" 19 #include "dt-bindings/gpio/gpio.h" 23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; 33 stdout-path = &uart0; 42 compatible = "gpio-keys-polled"; 43 poll-interval = <100>; 97 compatible = "gpio-leds"; [all …]
|
/linux/drivers/gpu/drm/amd/include/ |
H A D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,… 156 // Bit0:{=0:single, =1:dual}, 222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_… 433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_… 440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di… [all …]
|
/linux/drivers/gpu/drm/radeon/ |
H A D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 146 /* Bit0:{=0:single, =1:dual}, 214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_… 403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_… 410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di… 504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)… 536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode [all …]
|
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
H A D | dcn10_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 37 enc10->base.ctx 39 enc10->base.ctx->logger 42 (enc10->link_regs->reg) 46 enc10->link_shift->field_name, enc10->link_mask->field_name 52 * ASIC-dependent, actual values for register programming 98 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control() 100 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control() 170 /* For 10-bit PRBS or debug symbols in set_dp_phy_pattern_d102() 360 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT); in set_dp_phy_pattern_hbr2_compliance_cp2520_2() [all …]
|
/linux/drivers/gpu/drm/rockchip/ |
H A D | dw-mipi-dsi-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 274 /* dual-channel */ 288 unsigned int lane_mbps; /* per lane */ 365 return -EINVAL; in max_mbps_to_parameter() [all …]
|