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/linux/Documentation/devicetree/bindings/serial/
H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
19 - fsl,imx25-uart
[all …]
/linux/drivers/i2c/busses/
H A Di2c-sh_mobile.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
15 #include <linux/dma-mapping.h>
33 /* IRQ: DTE WAIT */
40 /* IRQ: DTE WAIT WAIT */
41 /* ICIC: -DTE */
47 /* IRQ: DTE WAIT WAIT WAIT */
48 /* ICIC: -DTE */
52 /* 3 bytes or more, +---------+ gets repeated */
[all …]
/linux/include/uapi/linux/
H A Datmsap.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* atmsap.h - ATM Service Access Point addressing definitions */
4 /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
24 #define ATM_L2_ISO1745 0x01 /* Basic mode ISO 1745 */
25 #define ATM_L2_Q291 0x02 /* ITU-T Q.291 (Rec. I.441) */
26 #define ATM_L2_X25_LL 0x06 /* ITU-T X.25, link layer */
27 #define ATM_L2_X25_ML 0x07 /* ITU-T X.25, multilink */
28 #define ATM_L2_LAPB 0x08 /* Extended LAPB, half-duplex (Rec. T.71) */
33 #define ATM_L2_X75 0x0d /* ITU-T X.75, SLP */
34 #define ATM_L2_Q922 0x0e /* ITU-T Q.922 */
[all …]
/linux/drivers/net/wan/
H A Dwanxl.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * - Only DTE (external clock) support with NRZ and NRZI encodings
10 * - wanXL100 will require minor driver modifications, no access to hw
29 #include <linux/dma-mapping.h>
42 /* MAILBOX #1 - PUTS COMMANDS */
45 #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
47 #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
50 /* MAILBOX #2 - DRAM SIZE */
57 int node; /* physical port #0 - 3 */
78 struct port ports[]; /* 1 - 4 port structures follow */
[all …]
H A Dhdlc_fr.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 1999 - 2006 Krzysztof Halasa <khc@pm.waw.pl>
11 DCE mode:
13 (exist,new) -> 0,0 when "PVC create" or if "link unreliable"
14 0,x -> 1,1 if "link reliable" when sending FULL STATUS
15 1,1 -> 1,0 if received FULL STATUS ACK
17 (active) -> 0 when "ifconfig PVC down" or "link unreliable" or "PVC create"
18 -> 1 when "PVC up" and (exist,new) = 1,0
20 DTE mode:
27 CCITT LMI: ITU-T Q.933 Annex A
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2018-2022 Toradex
16 compatible = "pwm-backlight";
17 brightness-levels = <0 4 8 16 32 64 128 255>;
18 default-brightness-level = <6>;
19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_bl_on>;
22 power-supply = <&reg_3v3>;
28 compatible = "gpio-usb-b-connector", "usb-b-connector";
[all …]
H A Dimx7-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2016-2022 Toradex
6 #include <dt-bindings/pwm/pwm.h>
15 brightness-levels = <0 45 63 88 119 158 203 255>;
16 compatible = "pwm-backlight";
17 default-brightness-level = <4>;
18 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_bl_on>;
21 power-supply = <&reg_module_3v3>;
[all …]
H A Dimx53-cx9020.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * based on imx53-qsb.dts
7 /dts-v1/;
15 stdout-path = &uart2;
24 display-0 {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 compatible = "fsl,imx-parallel-display";
28 interface-pix-fmt = "rgb24";
29 pinctrl-names = "default";
[all …]
H A Dimx7d-meerkat96.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 /dts-v1/;
12 compatible = "novtech,imx7d-meerkat96", "fsl,imx7d";
15 stdout-path = &uart6;
23 reg_wlreg_on: regulator-wlreg-on {
24 compatible = "regulator-fixed";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_wlreg_on>;
27 regulator-name = "wlreg_on";
28 regulator-min-microvolt = <3300000>;
[all …]
/linux/Documentation/networking/
H A Dgeneric-hdlc.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - Normal (routed) and Ethernet-bridged (Ethernet device emulation)
16 - ARP support (no InARP support in the kernel - there is an
17 experimental InARP user-space daemon available on:
20 2. raw HDLC - either IP (IPv4) interface or Ethernet device emulation
25 Generic HDLC is a protocol driver only - it needs a low-level driver
28 Ethernet device emulation (using HDLC or Frame-Relay PVC) is compatible
40 gcc -O2 -Wall -o sethdlc sethdlc.c
44 Use sethdlc to set physical interface, clock rate, HDLC mode used,
59 In Frame Relay mode, ifconfig master hdlc device up (without assigning
[all …]
H A Dlapb-module.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Changed (Henner Eisen, 2000-10-29): int return value for data_indication()
25 ----------
37 -----------------------------
59 ------------------------
74 unsigned int mode;
84 The mode variable is a bit field used for setting (at present) three values.
92 2 DTE/DCE operation (0=LAPB_DTE 1=LAPB_DCE)
93 3-31 Reserved, must be 0.
99 LAPB are different to indicate the mode of operation, the default is Single
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-pinmux
19 - description: tri-state registers
20 - description: mux register
21 - description: pull-up/down registers
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-trimslice.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
7 #include "tegra20-cpu-opp.dtsi"
20 stdout-path = "serial0:115200n8";
31 vdd-supply = <&hdmi_vdd_reg>;
32 pll-supply = <&hdmi_pll_reg>;
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
35 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
[all …]
H A Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
92 nvidia,pins = "dtb", "dtc", "dte";
206 "dtc", "dte", "gpu", "sdio1",
[all …]
H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
H A Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 lan-reset-n-hog {
32 gpio-hog;
34 output-high;
35 line-name = "LAN_RESET#";
38 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
[all …]
H A Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
H A Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-phycore-fpsc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
6 #include <dt-bindings/net/ti-dp83867.h>
10 compatible = "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
11 model = "PHYTEC phyCORE-i.MX8MP FPSC";
23 reg_usdhc2_vmmc: regulator-usdhc2 {
24 compatible = "regulator-fixed";
25 off-on-delay-us = <12000>;
26 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
27 pinctrl-names = "default";
28 regulator-max-microvolt = <3300000>;
[all …]
H A Dimx8mm-phyboard-polis-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include "imx8mm-phycore-som.dtsi"
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
20 stdout-path = &uart3;
[all …]
/linux/rust/kernel/net/phy/
H A Dreg.rs1 // SPDX-License-Identifier: GPL-2.0
45 fn read(&self, dev: &mut Device) -> Result<u16>; in read()
48 fn write(&self, dev: &mut Device, val: u16) -> Result; in write()
51 fn read_status(dev: &mut Device) -> Result<u16>; in read_status()
59 /// Basic mode control.
61 /// Basic mode status.
67 /// Auto-negotiation advertisement.
69 /// Auto-negotiation link partner base page ability.
71 /// Auto-negotiation expansion.
73 /// Auto-negotiation next page transmit.
[all …]
/linux/drivers/ata/
H A Dpata_rdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata_rdc - Driver for later RDC PATA controllers
6 * INCITS 370-2004 (1510D): ATA Host Adapter Standards
30 * rdc_pata_cable_detect - Probe host controller cable detect info
42 struct rdc_host_priv *hpriv = ap->host->private_data; in rdc_pata_cable_detect()
46 mask = 0x30 << (2 * ap->port_no); in rdc_pata_cable_detect()
47 if ((hpriv->saved_iocfg & mask) == 0) in rdc_pata_cable_detect()
53 * rdc_pata_prereset - prereset for PATA host controller
62 struct ata_port *ap = link->ap; in rdc_pata_prereset()
63 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in rdc_pata_prereset()
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
[all …]
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
[all …]

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