xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml (revision 69f2970aad93758bea863432e49b564e0ba649ca) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Display Port Controller
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Jitao shi <jitao.shi@mediatek.com>
12
13description: |
14  MediaTek DP and eDP are different hardwares and there are some features
15  which are not supported for eDP. For example, audio is not supported for
16  eDP. Therefore, we need to use two different compatibles to describe them.
17  In addition, We just need to enable the power domain of DP, so the clock
18  of DP is generated by itself and we are not using other PLL to generate
19  clocks.
20
21properties:
22  compatible:
23    enum:
24      - mediatek,mt8188-dp-tx
25      - mediatek,mt8188-edp-tx
26      - mediatek,mt8195-dp-tx
27      - mediatek,mt8195-edp-tx
28
29  reg:
30    maxItems: 1
31
32  nvmem-cells:
33    maxItems: 1
34    description: efuse data for display port calibration
35
36  nvmem-cell-names:
37    const: dp_calibration_data
38
39  power-domains:
40    maxItems: 1
41
42  interrupts:
43    maxItems: 1
44
45  '#sound-dai-cells':
46    const: 0
47
48  aux-bus:
49    $ref: /schemas/display/dp-aux-bus.yaml#
50
51  ports:
52    $ref: /schemas/graph.yaml#/properties/ports
53    properties:
54      port@0:
55        $ref: /schemas/graph.yaml#/properties/port
56        description: Input endpoint of the controller, usually dp_intf
57
58      port@1:
59        $ref: /schemas/graph.yaml#/$defs/port-base
60        unevaluatedProperties: false
61        description: Output endpoint of the controller
62        properties:
63          endpoint:
64            $ref: /schemas/media/video-interfaces.yaml#
65            unevaluatedProperties: false
66            properties:
67              data-lanes:
68                description: |
69                  number of lanes supported by the hardware.
70                  The possible values:
71                  0       - For 1 lane enabled in IP.
72                  0 1     - For 2 lanes enabled in IP.
73                  0 1 2 3 - For 4 lanes enabled in IP.
74                minItems: 1
75                maxItems: 4
76            required:
77              - data-lanes
78
79    required:
80      - port@0
81      - port@1
82
83  max-linkrate-mhz:
84    enum: [ 1620, 2700, 5400, 8100 ]
85    description: maximum link rate supported by the hardware.
86
87required:
88  - compatible
89  - reg
90  - interrupts
91  - ports
92  - max-linkrate-mhz
93
94allOf:
95  - $ref: /schemas/sound/dai-common.yaml#
96  - if:
97      not:
98        properties:
99          compatible:
100            contains:
101              enum:
102                - mediatek,mt8188-dp-tx
103                - mediatek,mt8195-dp-tx
104    then:
105      properties:
106        '#sound-dai-cells': false
107
108unevaluatedProperties: false
109
110examples:
111  - |
112    #include <dt-bindings/interrupt-controller/arm-gic.h>
113    #include <dt-bindings/power/mt8195-power.h>
114    dptx@1c600000 {
115        compatible = "mediatek,mt8195-dp-tx";
116        reg = <0x1c600000 0x8000>;
117        power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
118        interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
119        max-linkrate-mhz = <8100>;
120
121        ports {
122            #address-cells = <1>;
123            #size-cells = <0>;
124
125            port@0 {
126                reg = <0>;
127                dptx_in: endpoint {
128                    remote-endpoint = <&dp_intf0_out>;
129                };
130            };
131            port@1 {
132                reg = <1>;
133                dptx_out: endpoint {
134                    data-lanes = <0 1 2 3>;
135                };
136            };
137        };
138    };
139