| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_dpia.c | 66 DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
277 * - CR for the first hop (DPTX-to-DPIA) is assumed to be successful.
314 /* DPTX-to-DPIA */ in dpia_training_cr_non_transparent()
571 * - EQ for the first hop (DPTX-to-DPIA) is assumed to be successful.
609 /* DPTX-to-DPIA equalization always successful. */ in dpia_training_eq_non_transparent()
850 * (DPTX-to-DPIA) and last hop (DPRX).
868 if (hop == repeater_cnt) { /* DPTX-to-DPIA */ in dpia_training_end()
870 * DPTX-to-DPIA hop trained. No DPCD write needed for first hop. in dpia_training_end()
1007 /* Train each hop in turn starting with the one closest to DPTX. in dpia_perform_link_training()
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| H A D | link_dp_dpia_bw.c | 325 /* Send request acknowledgment to Turn ON DPTX support */ in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
334 DC_LOG_DEBUG("%s: FAILURE Enabling DPtx BW Allocation Mode Support for link(%d)\n", in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
337 // SUCCESS Enabled DPtx BW Allocation Mode Support in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
338 DC_LOG_DEBUG("%s: SUCCESS Enabling DPtx BW Allocation Mode Support for link(%d)\n", in link_dp_dpia_set_dptx_usb4_bw_alloc_support()
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| H A D | link_dp_training.c | 954 * AUX_RD_INTERVAL for DPTX-to-DPIA hop. in configure_lttpr_mode_non_transparent()
1510 * If the upstream DPTX and downstream DPRX both support TPS4, in dp_transition_to_video_idle()
1574 * Per DP specs starting from here, DPTX device shall not issue in dp_perform_link_training()
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | mt8195-mt6359.yaml | 60 mediatek,dptx-codec:
135 mediatek,dptx-codec: false
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| /linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | Makefile | 2 analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o analogix-i2c-dptx.o
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| H A D | analogix-i2c-dptx.c | 14 #include "analogix-i2c-dptx.h"
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| H A D | analogix-anx6345.c | 31 #include "analogix-i2c-dptx.h"
58 /* I2C Slave addresses of ANX6345 are mapped as DPTX and SYS */
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| H A D | analogix-anx78xx.h | 9 #include "analogix-i2c-dptx.h"
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| /linux/drivers/gpu/drm/mediatek/ |
| H A D | Kconfig | 28 tristate "DRM DPTX Support for MediaTek SoCs"
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| H A D | mtk_dp.c | 2729 "failed to request mediatek dptx irq\n"); in mtk_dp_probe()
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| /linux/drivers/gpu/drm/rockchip/ |
| H A D | cdn-dp-core.c | 49 #define CDN_DP_FIRMWARE "rockchip/dptx.bin"
154 int dptx; in cdn_dp_get_port_lanes() local
157 dptx = extcon_get_state(edev, EXTCON_DISP_DP); in cdn_dp_get_port_lanes()
158 if (dptx > 0) { in cdn_dp_get_port_lanes()
761 dp->dptx_rst = devm_reset_control_get(dev, "dptx"); in cdn_dp_parse_dt()
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| /linux/Documentation/devicetree/bindings/display/mediatek/ |
| H A D | mediatek,dp.yaml | 94 dptx@1c600000 {
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| /linux/Documentation/devicetree/bindings/display/rockchip/ |
| H A D | cdn-dp-rockchip.txt | 16 Required elements: "apb", "core", "dptx", "spdif"
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-cadence-torrent.yaml | 56 - description: Offset of the DPTX PHY configuration registers.
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| /linux/sound/soc/mediatek/mt8195/ |
| H A D | mt8195-dai-etdm.c | 1306 {"DPTX Playback", NULL, "DPTX_OUT_MUX"},
1308 {"ETDM_OUTPUT", NULL, "DPTX Playback"},
2369 /* dptx configure */ in mtk_dai_hdmitx_dptx_hw_params()
2412 /* enable dptx interface */ in mtk_dai_hdmitx_dptx_trigger()
2426 /* disable dptx interface */ in mtk_dai_hdmitx_dptx_trigger()
2521 .name = "DPTX",
2524 .stream_name = "DPTX Playback",
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| /linux/sound/soc/mediatek/mt8188/ |
| H A D | mt8188-mt6359.c | 153 SND_SOC_DAILINK_DEFS(dptx,
154 DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
1129 SND_SOC_DAILINK_REG(dptx),
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynosautov9.c | 502 /* DPTX */
672 /* DPTX */
829 /* DPTX */
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| H A D | clk-exynosautov920.c | 615 /* DPTX */
805 /* DPTX */
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp_link_training.c | 284 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read in intel_dp_init_lttpr_and_dprx_caps()
814 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate in intel_dp_prepare_link_train()
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| /linux/drivers/thunderbolt/ |
| H A D | tb.c | 2629 * makes the DPTX request fail on graphics side. in tb_alloc_dp_bandwidth()
2684 tb_port_dbg(in, "DPTX disabled bandwidth allocation mode\n"); in tb_handle_dp_bandwidth_request()
2701 tb_port_dbg(in, "DPTX enabled bandwidth allocation mode, updating estimated bandwidth\n"); in tb_handle_dp_bandwidth_request()
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| H A D | ctl.c | 796 name = "DPTX discovery"; in tb_cfg_ack_notification()
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8195-cherry.dtsi | 835 dptx_pin: dptx-default-pins {
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_detection.c | 1008 * - Enable BW ALLOC support on DPtx if applicable in detect_link_and_local_sink()
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | tc358767.c | 187 #define DP_EN BIT(0) /* Enable DPTX function */
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-base.dtsi | 615 reset-names = "spdif", "dptx", "apb", "core";
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