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Searched full:dptx (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-reg.h114 /* dptx phy addr */
123 /* dptx hpd addr */
151 /* dptx stream addr */
169 /* dptx glbl addr */
/linux/Documentation/devicetree/bindings/sound/
H A Dmt8195-mt6359.yaml63 mediatek,dptx-codec:
139 mediatek,dptx-codec: false
/linux/drivers/gpu/drm/bridge/analogix/
H A DMakefile2 analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o analogix-i2c-dptx.o
H A Danalogix-anx78xx.h9 #include "analogix-i2c-dptx.h"
/linux/drivers/gpu/drm/mediatek/
H A DKconfig25 tristate "DRM DPTX Support for MediaTek SoCs"
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dp.yaml114 dptx@1c600000 {
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_dpia_bw.c236 DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode enabled", __func__, link->link_index); in link_dpia_enable_usb4_dp_bw_alloc_mode()
261 …DC_LOG_DEBUG("%s: link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index); in link_dpia_enable_usb4_dp_bw_alloc_mode()
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-cadence-torrent.yaml56 - description: Offset of the DPTX PHY configuration registers.
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-dai-etdm.c1305 {"DPTX Playback", NULL, "DPTX_OUT_MUX"},
1307 {"ETDM_OUTPUT", NULL, "DPTX Playback"},
2404 /* dptx configure */ in mtk_dai_hdmitx_dptx_trigger()
2447 /* enable dptx interface */ in mtk_dai_hdmitx_dptx_set_sysclk()
2461 /* disable dptx interface */
2565 .name = "DPTX",
2568 .stream_name = "DPTX Playback",
/linux/drivers/clk/samsung/
H A Dclk-exynosautov9.c501 /* DPTX */
671 /* DPTX */
828 /* DPTX */
H A Dclk-exynosautov920.c622 /* DPTX */
812 /* DPTX */
/linux/drivers/thunderbolt/
H A Dtb.c2734 * makes the DPTX request fail on graphics side. in tb_alloc_dp_bandwidth()
2790 tb_port_dbg(in, "DPTX disabled bandwidth allocation mode\n"); in tb_handle_dp_bandwidth_request()
2807 tb_port_dbg(in, "DPTX enabled bandwidth allocation mode, updating estimated bandwidth\n"); in tb_handle_dp_bandwidth_request()
H A Dctl.c811 name = "DPTX discovery"; in tb_cfg_ack_notification()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c669 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read in intel_dp_init_lttpr_and_dprx_caps()
1304 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate in intel_dp_prepare_link_train()
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_display.c895 * Returns: where there is a display connected to the DPTX (returning in msm_dp_bridge_detect()