1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx ZynqMP DisplayPort Subsystem 8 9description: | 10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC) 11 implements the display and audio pipelines based on the DisplayPort v1.2 12 standard. The subsystem includes multiple functional blocks as below: 13 14 +------------------------------------------------------------+ 15 +--------+ | +----------------+ +-----------+ | 16 | DPDMA | --->| | --> | Video | Video +-------------+ | 17 | 4x vid | | | | | Rendering | -+--> | | | +------+ 18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ 20 | | and STC | +-----------+ | | Controller | | +------+ 21 Live Video --->| | --> | Audio | Audio | |---> | PHY1 | 22 | | | | Mixer | --+-> | | | +------+ 23 Live Audio --->| | --> | | || +-------------+ | 24 | +----------------+ +-----------+ || | 25 +---------------------------------------||-------------------+ 26 vv 27 Blended Video and 28 Mixed Audio to PL 29 30 The Buffer Manager interacts with external interface such as DMA engines or 31 live audio/video streams from the programmable logic. The Video Rendering 32 Pipeline blends the video and graphics layers and performs colorspace 33 conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort 34 Source Controller handles the DisplayPort protocol and connects to external 35 PHYs. 36 37 The subsystem supports 2 video and 2 audio streams, and various pixel formats 38 and depths up to 4K@30 resolution. 39 40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual" 41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf) 42 for more details. 43 44maintainers: 45 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 46 47properties: 48 compatible: 49 const: xlnx,zynqmp-dpsub-1.7 50 51 reg: 52 maxItems: 4 53 reg-names: 54 items: 55 - const: dp 56 - const: blend 57 - const: av_buf 58 - const: aud 59 60 interrupts: 61 maxItems: 1 62 63 clocks: 64 description: 65 The APB clock and at least one video clock are mandatory, the audio clock 66 is optional. 67 minItems: 2 68 items: 69 - description: dp_apb_clk is the APB clock 70 - description: dp_aud_clk is the Audio clock 71 - description: 72 dp_vtc_pixel_clk_in is the non-live video clock (from Processing 73 System) 74 - description: 75 dp_live_video_in_clk is the live video clock (from Programmable 76 Logic) 77 clock-names: 78 oneOf: 79 - minItems: 2 80 items: 81 - const: dp_apb_clk 82 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 83 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 84 - minItems: 3 85 items: 86 - const: dp_apb_clk 87 - const: dp_aud_clk 88 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 89 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ] 90 91 power-domains: 92 maxItems: 1 93 94 resets: 95 maxItems: 1 96 97 dmas: 98 items: 99 - description: Video layer, plane 0 (RGB or luma) 100 - description: Video layer, plane 1 (U/V or U) 101 - description: Video layer, plane 2 (V) 102 - description: Graphics layer 103 - description: Audio channel 0 104 - description: Audio channel 1 105 dma-names: 106 items: 107 - const: vid0 108 - const: vid1 109 - const: vid2 110 - const: gfx0 111 - const: aud0 112 - const: aud1 113 114 phys: 115 description: PHYs for the DP data lanes 116 minItems: 1 117 maxItems: 2 118 phy-names: 119 minItems: 1 120 items: 121 - const: dp-phy0 122 - const: dp-phy1 123 124 ports: 125 $ref: /schemas/graph.yaml#/properties/ports 126 description: | 127 Connections to the programmable logic and the DisplayPort PHYs. Each port 128 shall have a single endpoint. 129 130 properties: 131 port@0: 132 $ref: /schemas/graph.yaml#/properties/port 133 description: The live video input from the programmable logic 134 135 port@1: 136 $ref: /schemas/graph.yaml#/properties/port 137 description: The live graphics input from the programmable logic 138 139 port@2: 140 $ref: /schemas/graph.yaml#/properties/port 141 description: The live audio input from the programmable logic 142 143 port@3: 144 $ref: /schemas/graph.yaml#/properties/port 145 description: The blended video output to the programmable logic 146 147 port@4: 148 $ref: /schemas/graph.yaml#/properties/port 149 description: The mixed audio output to the programmable logic 150 151 port@5: 152 $ref: /schemas/graph.yaml#/properties/port 153 description: The DisplayPort output 154 155 required: 156 - port@0 157 - port@1 158 - port@2 159 - port@3 160 - port@4 161 - port@5 162 163required: 164 - compatible 165 - reg 166 - reg-names 167 - interrupts 168 - clocks 169 - clock-names 170 - power-domains 171 - resets 172 - dmas 173 - dma-names 174 - phys 175 - phy-names 176 - ports 177 178additionalProperties: false 179 180examples: 181 - | 182 #include <dt-bindings/phy/phy.h> 183 #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 184 185 display@fd4a0000 { 186 compatible = "xlnx,zynqmp-dpsub-1.7"; 187 reg = <0xfd4a0000 0x1000>, 188 <0xfd4aa000 0x1000>, 189 <0xfd4ab000 0x1000>, 190 <0xfd4ac000 0x1000>; 191 reg-names = "dp", "blend", "av_buf", "aud"; 192 interrupts = <0 119 4>; 193 interrupt-parent = <&gic>; 194 195 clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk"; 196 clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>; 197 198 power-domains = <&pd_dp>; 199 resets = <&reset ZYNQMP_RESET_DP>; 200 201 dma-names = "vid0", "vid1", "vid2", "gfx0", "aud0", "aud1"; 202 dmas = <&xlnx_dpdma 0>, 203 <&xlnx_dpdma 1>, 204 <&xlnx_dpdma 2>, 205 <&xlnx_dpdma 3>, 206 <&xlnx_dpdma 4>, 207 <&xlnx_dpdma 5>; 208 209 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 210 <&psgtr 0 PHY_TYPE_DP 1 3>; 211 212 phy-names = "dp-phy0", "dp-phy1"; 213 214 ports { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 port@0 { 219 reg = <0>; 220 }; 221 port@1 { 222 reg = <1>; 223 }; 224 port@2 { 225 reg = <2>; 226 }; 227 port@3 { 228 reg = <3>; 229 }; 230 port@4 { 231 reg = <4>; 232 }; 233 port@5 { 234 reg = <5>; 235 dpsub_dp_out: endpoint { 236 remote-endpoint = <&dp_connector>; 237 }; 238 }; 239 }; 240 }; 241 242... 243