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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analogix DP (Display Port) core interface driver.
40 static void analogix_dp_init_dp(struct analogix_dp_device *dp) in analogix_dp_init_dp() argument
42 analogix_dp_reset(dp); in analogix_dp_init_dp()
44 analogix_dp_swreset(dp); in analogix_dp_init_dp()
46 analogix_dp_init_analog_param(dp); in analogix_dp_init_dp()
47 analogix_dp_init_interrupt(dp); in analogix_dp_init_dp()
50 analogix_dp_enable_sw_function(dp); in analogix_dp_init_dp()
52 analogix_dp_config_interrupt(dp); in analogix_dp_init_dp()
54 analogix_dp_init_hpd(dp); in analogix_dp_init_dp()
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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_drm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
19 * msm_dp_bridge_detect - callback to determine if connector is connected
24 msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) in msm_dp_bridge_detect() argument
26 struct msm_dp *dp; in msm_dp_bridge_detect() local
28 dp = to_dp_bridge(bridge)->msm_dp_display; in msm_dp_bridge_detect()
30 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in msm_dp_bridge_detect()
31 str_true_false(dp->link_ready)); in msm_dp_bridge_detect()
33 return (dp->link_ready) ? connector_status_connected : in msm_dp_bridge_detect()
42 struct msm_dp *dp; in msm_dp_bridge_atomic_check() local
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H A Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
33 MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays");
190 { .compatible = "qcom,sa8775p-dp", .data = &msm_dp_desc_sa8775p },
191 { .compatible = "qcom,sc7180-dp", .data = &msm_dp_desc_sc7180 },
192 { .compatible = "qcom,sc7280-dp", .data = &msm_dp_desc_sc7280 },
193 { .compatible = "qcom,sc7280-edp", .data = &msm_dp_desc_sc7280 },
194 { .compatible = "qcom,sc8180x-dp", .data = &msm_dp_desc_sc8180x },
195 { .compatible = "qcom,sc8180x-edp", .data = &msm_dp_desc_sc8180x },
196 { .compatible = "qcom,sc8280xp-dp", .data = &msm_dp_desc_sc8280xp },
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_dp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Samsung SoC DP (Display Port) interface driver.
38 struct drm_connector *connector; member
51 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_crtc_clock_enable() local
52 struct drm_encoder *encoder = &dp->encoder; in exynos_dp_crtc_clock_enable()
54 if (!encoder->crtc) in exynos_dp_crtc_clock_enable()
55 return -EPERM; in exynos_dp_crtc_clock_enable()
57 exynos_drm_pipe_clk_enable(to_exynos_crtc(encoder->crtc), enable); in exynos_dp_crtc_clock_enable()
73 struct drm_connector *connector) in exynos_dp_get_modes() argument
75 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_get_modes() local
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/linux/drivers/gpu/drm/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for MegaChips STDP4028 with GE B850v3 firmware (LVDS-DP)
4 * Driver for MegaChips STDP2690 with GE B850v3 firmware (DP-DP++)
10 * This driver creates a drm_bridge and a drm_connector for the LVDS to DP++
12 * signal pipeline: a STDP4028(LVDS to DP) and a STDP2690(DP to DP++). The
19 * Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
60 struct drm_connector connector; member
71 struct i2c_adapter *adapter = client->adapter; in stdp2690_read_block()
76 .addr = client->addr, in stdp2690_read_block()
81 .addr = client->addr, in stdp2690_read_block()
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H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
290 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
299 #define DP_PHY_CFG_WR 0x0810 /* DP PHY Configuration Test Write Register */
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/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
16 #include <sound/hdmi-codec.h>
27 #include "cdn-dp-core.h"
28 #include "cdn-dp-reg.h"
63 { .compatible = "rockchip,rk3399-cdn-dp",
70 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
75 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
77 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
81 ret = regmap_write(dp->grf, reg, val); in cdn_dp_grf_write()
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
25 - PHY_TYPE_USB3
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H A Drockchip,rk3399-typec-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3399-typec-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Type-C PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-typec-phy
22 clock-names:
24 - const: tcpdcore
25 - const: tcpdphy-ref
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/linux/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_drv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 #include <linux/i2c-algo-bit.h>
23 #include "dp/dp_hw.h"
31 struct drm_connector connector; member
45 struct hibmc_dp dp; member
48 static inline struct hibmc_vdac *to_hibmc_vdac(struct drm_connector *connector) in to_hibmc_vdac() argument
50 return container_of(connector, struct hibmc_vdac, connector); in to_hibmc_vdac()
53 static inline struct hibmc_dp *to_hibmc_dp(struct drm_connector *connector) in to_hibmc_dp() argument
55 return container_of(connector, struct hibmc_dp, connector); in to_hibmc_dp()
71 int hibmc_ddc_create(struct drm_device *drm_dev, struct hibmc_vdac *connector);
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence MHDP8546 DP bridge driver.
7 * Authors: Quentin Schulz <quentin.schulz@free-electrons.com>
14 * - Implement optimized mailbox communication using mailbox interrupts
15 * - Add support for power management
16 * - Add support for features like audio, MST and fast link training
17 * - Implement request_fw_cancel to handle HW_STATE
18 * - Fix asynchronous loading of firmware implementation
19 * - Add DRM helper function for cdns_mhdp_lower_link_rate
29 #include <linux/media-bus-format.h>
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 enc110->base.ctx
59 enc110->base.ctx->logger
62 (enc110->link_regs->reg)
65 (enc110->aux_regs->reg)
68 (enc110->hpd_regs->reg)
75 * ASIC-dependent, actual values for register programming
91 (reg + enc110->offsets.dig)
94 (reg + enc110->offsets.dp)
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_encoders.c2 * Copyright 2007-11 Advanced Micro Devices, Inc.
74 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_get_backlight_level()
77 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_get_backlight_level()
87 struct drm_encoder *encoder = &amdgpu_encoder->base; in amdgpu_atombios_encoder_set_backlight_level()
88 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_set_backlight_level()
92 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_set_backlight_level()
95 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && in amdgpu_atombios_encoder_set_backlight_level()
96 amdgpu_encoder->enc_priv) { in amdgpu_atombios_encoder_set_backlight_level()
97 dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_encoder_set_backlight_level()
98 dig->backlight_level = level; in amdgpu_atombios_encoder_set_backlight_level()
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H A Damdgpu_pll.c33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
91 if (adev->family == AMDGPU_FAMILY_SI) in amdgpu_pll_get_fb_ref_div()
108 * amdgpu_pll_compute - compute PLL paramaters
131 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? in amdgpu_pll_compute()
141 fb_div_min = pll->min_feedback_div; in amdgpu_pll_compute()
142 fb_div_max = pll->max_feedback_div; in amdgpu_pll_compute()
144 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { in amdgpu_pll_compute()
150 if (pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
151 ref_div_min = pll->reference_div; in amdgpu_pll_compute()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_pps.h1 /* SPDX-License-Identifier: MIT */
23 #define with_intel_pps_lock(dp, wf) \ argument
24 for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf)))
28 void intel_pps_backlight_power(struct intel_connector *connector, bool enable);
61 void intel_pps_connector_debugfs_add(struct intel_connector *connector);
H A Dintel_dp_aux_backlight.c27 * backlight through DP AUX can actually use two different interfaces: Intel's
28 * proprietary DP AUX backlight interface, and the standard VESA backlight
46 * DP AUX registers for Intel's proprietary HDR backlight interface. We define
98 INTEL_DP_AUX_BACKLIGHT_AUTO = -1,
112 intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) in intel_dp_aux_supports_hdr_backlight() argument
114 struct intel_display *display = to_intel_display(connector); in intel_dp_aux_supports_hdr_backlight()
115 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); in intel_dp_aux_supports_hdr_backlight()
116 struct drm_dp_aux *aux = &intel_dp->aux; in intel_dp_aux_supports_hdr_backlight()
117 struct intel_panel *panel = &connector->panel; in intel_dp_aux_supports_hdr_backlight()
127 drm_dbg_kms(display->drm, in intel_dp_aux_supports_hdr_backlight()
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/linux/Documentation/devicetree/bindings/display/
H A Ddp-aux-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
16 particular, DP sinks support DDC over DP AUX which allows tunneling
19 To model this relationship, DP sinks should be placed as children
20 of the DP controller under the "aux-bus" node.
23 possible it will be extended in the future to handle the DP case.
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/linux/drivers/gpu/drm/radeon/
H A Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
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/linux/drivers/usb/typec/ucsi/
H A Ducsi_yoga_c630.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022-2024, Linaro Ltd
18 #include <linux/platform_data/lenovo-yoga-c630.h>
21 #include <drm/bridge/aux-bridge.h>
45 *version = uec->version; in yoga_c630_ucsi_read_version()
56 ret = yoga_c630_ec_ucsi_read(uec->ec, buf); in yoga_c630_ucsi_read_cci()
72 ret = yoga_c630_ec_ucsi_read(uec->ec, buf); in yoga_c630_ucsi_read_message_in()
86 return yoga_c630_ec_ucsi_write(uec->ec, (u8*)&command); in yoga_c630_ucsi_async_control()
97 * EC doesn't return connector's DP mode even though it is supported. in yoga_c630_ucsi_sync_control()
109 dev_dbg(ucsi->dev, "faking DP altmode for con1\n"); in yoga_c630_ucsi_sync_control()
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/media-bus-format.h>
42 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
49 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
249 * struct zynqmp_dp_link_config - Common link config between source and sink
259 * struct zynqmp_dp_mode - Configured mode of DisplayPort
273 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
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/linux/Documentation/driver-api/media/drivers/
H A Dtuners.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------------------
12 - L= LG_API (VHF_LO=0x01, VHF_HI=0x02, UHF=0x08, radio=0x04)
13 - P= PHILIPS_API (VHF_LO=0xA0, VHF_HI=0x90, UHF=0x30, radio=0x04)
14 - T= TEMIC_API (VHF_LO=0x02, VHF_HI=0x04, UHF=0x01)
15 - A= ALPS_API (VHF_LO=0x14, VHF_HI=0x12, UHF=0x11)
16 - M= PHILIPS_MK3 (VHF_LO=0x01, VHF_HI=0x02, UHF=0x04, radio=0x19)
19 -------------------
21 - Samsung Tuner identification: (e.g. TCPM9091PD27)
23 .. code-block:: none
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/linux/drivers/platform/x86/
H A Dmeegopad_anx7428.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver to power on the Analogix ANX7428 USB Type-C crosspoint switch
4 * on MeeGoPad top-set boxes.
6 * The MeeGoPad T8 and T9 are Cherry Trail top-set boxes which
7 * use an ANX7428 to provide a Type-C port with USB3.1 Gen 1 and
8 * DisplayPort over Type-C alternate mode support.
12 * to send the right signal to the 4 highspeed pairs of the Type-C
13 * connector. It also takes care of HPD and AUX channel routing for
14 * DP alternate mode.
16 * IOW the ANX7428 operates fully autonomous and to the x5-Z8350 SoC
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
21 clock-names: true
25 phy-names:
26 const: dp
28 force-hpd:
34 hpd-gpios:
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn401/
H A Ddcn401_dio_link_encoder.c44 enc10->base.ctx
46 enc10->base.ctx->logger
49 (enc10->link_regs->reg)
53 enc10->link_shift->field_name, enc10->link_mask->field_name
56 (enc10->aux_regs->reg)
73 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 in enc401_hw_init()
74 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 in enc401_hw_init()
75 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 in enc401_hw_init()
76 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 in enc401_hw_init()
77 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 in enc401_hw_init()
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos5-dp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
17 const: samsung,exynos5-dp
25 clock-names:
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