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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_hdcp.c1 /* SPDX-License-Identifier: MIT */
39 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector *connector, in intel_dp_hdcp_wait_for_cp_irq() argument
42 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in intel_dp_hdcp_wait_for_cp_irq()
43 struct intel_dp *dp = &dig_port->dp; in intel_dp_hdcp_wait_for_cp_irq() local
44 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; in intel_dp_hdcp_wait_for_cp_irq()
47 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) in intel_dp_hdcp_wait_for_cp_irq()
48 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, in intel_dp_hdcp_wait_for_cp_irq()
52 drm_dbg_kms(connector->base.dev, in intel_dp_hdcp_wait_for_cp_irq()
60 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_write_an_aksv()
65 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, in intel_dp_hdcp_write_an_aksv()
[all …]
H A Dintel_dp.c93 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
95 /* DP DSC throughput values used for slice count calculations KPixels/s */
103 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
113 /* Constants for DP DSC configurations */
122 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
123 * @intel_dp: DP struct
125 * If a CPU or PCH DP output is attached to an eDP panel, this function
134 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
142 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
146 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
[all …]
H A Dintel_dp_mst.c58 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_dp_mst_max_dpt_bpp()
60 &crtc_state->hw.adjusted_mode; in intel_dp_mst_max_dpt_bpp()
66 * DSC->DPT interface width: in intel_dp_mst_max_dpt_bpp()
67 * ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used) in intel_dp_mst_max_dpt_bpp()
74 * testing on MTL-P the in intel_dp_mst_max_dpt_bpp()
75 * - DELL U3224KBA display in intel_dp_mst_max_dpt_bpp()
76 * - Unigraf UCD-500 CTS test sink in intel_dp_mst_max_dpt_bpp()
78 * - 5120x2880/995.59Mhz in intel_dp_mst_max_dpt_bpp()
79 * - 6016x3384/1357.23Mhz in intel_dp_mst_max_dpt_bpp()
80 * - 6144x3456/1413.39Mhz in intel_dp_mst_max_dpt_bpp()
[all …]
H A Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
48 #include <media/cec-notifier.h>
71 /* these are outputs from the chip - integrated only
89 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
105 * create the DMA scatter-gather list for each FB color plane. This sg
117 * in the rotated and remapped GTT view all no-CCS formats (up to 2
172 struct intel_connector *connector);
216 /* Read out the current hw state of this connector, returning true if
221 * state. This must be called _after_ display->get_pipe_config has
222 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
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H A Dintel_hotplug.c53 * intel_dp_hpd_pulse() via hooks, which handles DP short pulses and DP MST long
54 * pulses, with failures and non-MST long pulses triggering regular hotplug
55 * processing on the connector.
57 * The regular hotplug work function i915_hotplug_work_func() calls connector
58 * detect hooks, and, if connector status changes, triggers sending of hotplug
67 * while before being re-enabled. The intention is to mitigate issues raising
72 * seen when display port sink is connected, hence on platforms whose DP
75 * this is specific to DP sinks handled by this routine and any other display
81 * intel_hpd_pin_default - return default pin associated with certain port.
92 return HPD_PORT_A + port - PORT_A; in intel_hpd_pin_default()
[all …]
H A Dintel_ddi.c99 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
101 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
119 * DP/eDP/FDI use cases.
124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
127 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
130 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
136 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
141 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
143 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_drm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
17 * dp_bridge_detect - callback to determine if connector is connected
23 struct msm_dp *dp; in dp_bridge_detect() local
25 dp = to_dp_bridge(bridge)->dp_display; in dp_bridge_detect()
27 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in dp_bridge_detect()
28 (dp->link_ready) ? "true" : "false"); in dp_bridge_detect()
30 return (dp->link_ready) ? connector_status_connected : in dp_bridge_detect()
39 struct msm_dp *dp; in dp_bridge_atomic_check() local
41 dp = to_dp_bridge(bridge)->dp_display; in dp_bridge_atomic_check()
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dexynos_dp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Samsung SoC DP (Display Port) interface driver.
38 struct drm_connector *connector; member
51 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_crtc_clock_enable() local
52 struct drm_encoder *encoder = &dp->encoder; in exynos_dp_crtc_clock_enable()
54 if (!encoder->crtc) in exynos_dp_crtc_clock_enable()
55 return -EPERM; in exynos_dp_crtc_clock_enable()
57 exynos_drm_pipe_clk_enable(to_exynos_crtc(encoder->crtc), enable); in exynos_dp_crtc_clock_enable()
73 struct drm_connector *connector) in exynos_dp_get_modes() argument
75 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_get_modes() local
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c34 MODULE_PARM_DESC(mst, "Enable DisplayPort multi-stream (default: enabled)");
39 nouveau_dp_has_sink_count(struct drm_connector *connector, in nouveau_dp_has_sink_count() argument
42 return drm_dp_read_sink_count_cap(connector, outp->dp.dpcd, &outp->dp.desc); in nouveau_dp_has_sink_count()
51 ret = nvif_outp_dp_aux_xfer(&outp->outp, DP_AUX_NATIVE_READ, &size, in nouveau_dp_probe_lttpr()
64 struct drm_connector *connector = &nv_connector->base; in nouveau_dp_probe_dpcd() local
65 struct drm_dp_aux *aux = &nv_connector->aux; in nouveau_dp_probe_dpcd()
69 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd()
71 outp->dp.lttpr.nr = 0; in nouveau_dp_probe_dpcd()
72 outp->dp.rate_nr = 0; in nouveau_dp_probe_dpcd()
73 outp->dp.link_nr = 0; in nouveau_dp_probe_dpcd()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for MegaChips STDP4028 with GE B850v3 firmware (LVDS-DP)
4 * Driver for MegaChips STDP2690 with GE B850v3 firmware (DP-DP++)
10 * This driver creates a drm_bridge and a drm_connector for the LVDS to DP++
12 * signal pipeline: a STDP4028(LVDS to DP) and a STDP2690(DP to DP++). The
19 * Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
60 struct drm_connector connector; member
71 struct i2c_adapter *adapter = client->adapter; in stdp2690_read_block()
76 .addr = client->addr, in stdp2690_read_block()
81 .addr = client->addr, in stdp2690_read_block()
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H A Ddisplay-connector.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/media-bus-format.h>
39 return flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR ? 0 : -EINVAL; in display_connector_attach()
47 if (conn->hpd_gpio) { in display_connector_detect()
48 if (gpiod_get_value_cansleep(conn->hpd_gpio)) in display_connector_detect()
54 if (conn->bridge.ddc && drm_probe_ddc(conn->bridge.ddc)) in display_connector_detect()
57 switch (conn->bridge.type) { in display_connector_detect()
74 * Composite and S-Video connectors have no other detection in display_connector_detect()
85 struct drm_connector *connector) in display_connector_edid_read() argument
89 return drm_edid_read_ddc(connector, conn->bridge.ddc); in display_connector_edid_read()
[all …]
/linux/Documentation/devicetree/bindings/display/connector/
H A Ddp-connector.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/connector/dp-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DisplayPort Connector
10 - Tomi Valkeinen <tomi.valkeinen@ti.com>
14 const: dp-connector
20 - full-size
21 - mini
23 hpd-gpios:
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/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c45 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
65 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_transaction()
68 ret = (*algo_data->aux_ch)(adapter, mode, in i2c_algo_dp_aux_transaction()
85 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_address()
92 algo_data->address = address; in i2c_algo_dp_aux_address()
93 algo_data->running = true; in i2c_algo_dp_aux_address()
104 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; in i2c_algo_dp_aux_stop()
111 if (algo_data->running) { in i2c_algo_dp_aux_stop()
113 algo_data->running = false; in i2c_algo_dp_aux_stop()
119 * I2C link must be running or this returns -EIO
[all …]
/linux/include/drm/bridge/
H A Danalogix_dp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Analogix DP (Display Port) Core interface driver.
29 struct drm_connector *connector; member
40 int analogix_dp_resume(struct analogix_dp_device *dp);
41 int analogix_dp_suspend(struct analogix_dp_device *dp);
45 int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev);
46 void analogix_dp_unbind(struct analogix_dp_device *dp);
48 int analogix_dp_start_crc(struct drm_connector *connector);
49 int analogix_dp_stop_crc(struct drm_connector *connector);
/linux/drivers/gpu/drm/display/
H A Ddrm_dp_cec.c1 // SPDX-License-Identifier: GPL-2.0
3 * DisplayPort CEC-Tunneling-over-AUX support
20 * Unfortunately it turns out that we have a chicken-and-egg situation
21 * here. Quite a few active (mini-)DP-to-HDMI or USB-C-to-HDMI adapters
22 * have a converter chip that supports CEC-Tunneling-over-AUX (usually the
24 * useless. Note that MegaChips 2900-based adapters appear to have good
42 * https://hverkuil.home.xs4all.nl/cec-status.txt
55 * DOC: dp cec helpers
57 * These functions take care of supporting the CEC-Tunneling-over-AUX
58 * feature of DisplayPort-to-HDMI adapters.
[all …]
/linux/drivers/gpu/drm/ast/
H A Dast_dp.c1 // SPDX-License-Identifier: GPL-2.0
31 return -EIO; /* extension headers not supported */ in ast_astdp_read_edid_block()
35 * by acquiring the I/O-register lock. in ast_astdp_read_edid_block()
37 mutex_lock(&ast->modeset_lock); in ast_astdp_read_edid_block()
50 ret = -EIO; in ast_astdp_read_edid_block()
56 * CRE4[7:0]: Read-Pointer for EDID (Unit: 4bytes); valid range: 0~64 in ast_astdp_read_edid_block()
72 * of right-click of mouse. in ast_astdp_read_edid_block()
87 ret = -EBUSY; in ast_astdp_read_edid_block()
98 * For 128-bytes EDID_1.3, in ast_astdp_read_edid_block()
99 * 1. Add the value of Bytes-126 to Bytes-127. in ast_astdp_read_edid_block()
[all …]
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence MHDP8546 DP bridge driver.
7 * Authors: Quentin Schulz <quentin.schulz@free-electrons.com>
14 * - Implement optimized mailbox communication using mailbox interrupts
15 * - Add support for power management
16 * - Add support for features like audio, MST and fast link training
17 * - Implement request_fw_cancel to handle HW_STATE
18 * - Fix asynchronous loading of firmware implementation
19 * - Add DRM helper function for cdns_mhdp_lower_link_rate
29 #include <linux/media-bus-format.h>
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 enc110->base.ctx
59 enc110->base.ctx->logger
62 (enc110->link_regs->reg)
65 (enc110->aux_regs->reg)
68 (enc110->hpd_regs->reg)
75 * ASIC-dependent, actual values for register programming
91 (reg + enc110->offsets.dig)
94 (reg + enc110->offsets.dp)
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_encoders.c2 * Copyright 2007-11 Advanced Micro Devices, Inc.
74 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_get_backlight_level()
77 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_get_backlight_level()
87 struct drm_encoder *encoder = &amdgpu_encoder->base; in amdgpu_atombios_encoder_set_backlight_level()
88 struct drm_device *dev = amdgpu_encoder->base.dev; in amdgpu_atombios_encoder_set_backlight_level()
92 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) in amdgpu_atombios_encoder_set_backlight_level()
95 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && in amdgpu_atombios_encoder_set_backlight_level()
96 amdgpu_encoder->enc_priv) { in amdgpu_atombios_encoder_set_backlight_level()
97 dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_encoder_set_backlight_level()
98 dig->backlight_leve in amdgpu_atombios_encoder_set_backlight_level()
305 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); amdgpu_atombios_encoder_mode_fixup() local
441 struct drm_connector *connector; amdgpu_atombios_encoder_get_encoder_mode() local
567 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); amdgpu_atombios_encoder_setup_dig_encoder() local
756 struct drm_connector *connector; amdgpu_atombios_encoder_setup_dig_transmitter() local
1143 amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector * connector,int action) amdgpu_atombios_encoder_set_edp_panel_power() argument
1199 struct drm_connector *connector; amdgpu_atombios_encoder_setup_external_encoder() local
1300 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); amdgpu_atombios_encoder_setup_dig() local
1495 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); amdgpu_atombios_encoder_set_crtc_source() local
1563 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); amdgpu_atombios_encoder_set_crtc_source() local
1668 amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder * encoder,struct drm_connector * connector) amdgpu_atombios_encoder_dac_load_detect() argument
1718 amdgpu_atombios_encoder_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector) amdgpu_atombios_encoder_dac_detect() argument
1757 amdgpu_atombios_encoder_dig_detect(struct drm_encoder * encoder,struct drm_connector * connector) amdgpu_atombios_encoder_dig_detect() argument
1813 amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected) amdgpu_atombios_encoder_set_bios_scratch_regs() argument
[all...]
H A Damdgpu_pll.c33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
91 if (adev->family == AMDGPU_FAMILY_SI) in amdgpu_pll_get_fb_ref_div()
108 * amdgpu_pll_compute - compute PLL paramaters
131 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? in amdgpu_pll_compute()
141 fb_div_min = pll->min_feedback_div; in amdgpu_pll_compute()
142 fb_div_max = pll->max_feedback_div; in amdgpu_pll_compute()
144 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { in amdgpu_pll_compute()
150 if (pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
151 ref_div_min = pll->reference_di in amdgpu_pll_compute()
[all...]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx78xx.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "analogix-anx78xx.h"
71 struct drm_connector connector; member
90 return container_of(c, struct anx78xx, connector); in connector_to_anx78xx()
112 return anx_dp_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg); in anx78xx_aux_transfer()
119 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_set_hpd()
124 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, in anx78xx_set_hpd()
136 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, in anx78xx_clear_hpd()
141 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], in anx78xx_clear_hpd()
163 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, in anx78xx_rx_initialization()
[all …]
H A Danalogix-anx6345.c1 /* SPDX-License-Identifier: GPL-2.0-only */
31 #include "analogix-i2c-dptx.h"
32 #include "analogix-i2c-txcommon.h"
51 struct drm_connector connector; member
70 return container_of(c, struct anx6345, connector); in connector_to_anx6345()
93 return anx_dp_aux_transfer(anx6345->map[I2C_IDX_DPTX], msg); in anx6345_aux_transfer()
102 err = anx6345_clear_bits(anx6345->map[I2C_IDX_TXCOM], in anx6345_dp_link_training()
108 err = drm_dp_dpcd_readb(&anx6345->aux, DP_MAX_LINK_RATE, &dp_bw); in anx6345_dp_link_training()
118 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw); in anx6345_dp_link_training()
119 return -EINVAL; in anx6345_dp_link_training()
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Ddp-aux-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
16 particular, DP sinks support DDC over DP AUX which allows tunneling
19 To model this relationship, DP sinks should be placed as children
20 of the DP controller under the "aux-bus" node.
23 possible it will be extended in the future to handle the DP case.
[all …]
/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
25 #include <linux/media-bus-format.h>
40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
266 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 enc10->base.ctx
39 enc10->base.ctx->logger
42 (enc10->link_regs->reg)
46 enc10->link_shift->field_name, enc10->link_mask->field_name
52 * ASIC-dependent, actual values for register programming
98 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control()
100 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
109 /* This register resides in DP back end block; in enable_phy_bypass_mode()
120 /* This register resides in DP back end block; in disable_prbs_symbols()
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