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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-timer-stm328 - "reset"
11 - "enable"
14 - "update"
18 - "compare_pulse"
21 - "OC1REF"
23 - "OC2REF"
25 - "OC3REF"
27 - "OC4REF"
32 - "OC5REF"
34 - "OC6REF"
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H A Dsysfs-class-net35 Values vary based on the lower-level protocol used by the
54 01-80-C2-00-00-0X on a bridge device. Only values that set bits
62 0 01-80-C2-00-00-00 Bridge Group Address used for STP
63 1 01-80-C2-00-00-01 (MAC Control) 802.3 used for MAC PAUSE
64 2 01-80-C2-00-00-02 (Link Aggregation) 802.3ad
68 care when forwarding control frames e.g. 802.1X-PAE or LLDP.
88 0 physical link is down
135 the device is not usable unless some supplicant-based
193 Indicates the system-wide interface unique index identifier as a
204 Indicates the system-wide interface unique index identifier a
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/linux/Documentation/admin-guide/device-mapper/
H A Ddm-flakey.rst2 dm-flakey
10 <up interval> seconds, then exhibits unreliable behaviour for <down
13 Also, consider using this in combination with the dm-delay target too,
18 ----------------
22 <dev path> <offset> <up interval> <down interval> \
28 Full pathname to the underlying block-device, or a
29 "major:minor" device-number.
34 <down interval>:
55 During <down interval>, replace <Nth_byte> of the data of
60 Counting starts at 1, to replace the first byte.
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/linux/Documentation/devicetree/bindings/pwm/
H A Drenesas,rzg2l-gpt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
16 * Up-counting or down-counting (saw waves) or up/down-counting
31 * Starting, stopping, clearing and up/down counters in response to input
33 * Starting, clearing, stopping and up/down counters in response to a
36 short-circuits between output pins.
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/linux/drivers/watchdog/
H A Dsunplus_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
33 #define DEVICE_NAME "sunplus-wdt"
55 void __iomem *base = priv->base; in sp_wdt_restart()
69 void __iomem *base = priv->base; in sp_wdt_ping()
72 if (wdev->timeout > SP_WDT_MAX_TIMEOUT) { in sp_wdt_ping()
73 /* WDT_CONMAX sets the count to the maximum (down-counting). */ in sp_wdt_ping()
78 * Watchdog timer is a 20-bit down-counting based on STC_CLK. in sp_wdt_ping()
82 count = (wdev->timeout * STC_CLK) >> 4; in sp_wdt_ping()
93 void __iomem *base = priv->base; in sp_wdt_stop()
103 void __iomem *base = priv->base; in sp_wdt_start()
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H A Drzv2h_wdt.c1 // SPDX-License-Identifier: GPL-2.0
83 * The down-counter is refreshed and starts counting operation on in rzv2h_wdt_ping()
86 writeb(0x0, priv->base + WDTRR); in rzv2h_wdt_ping()
87 writeb(0xFF, priv->base + WDTRR); in rzv2h_wdt_ping()
94 u32 reg = readl(priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_stop()
96 writel(reg | WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_stop()
101 u32 reg = readl(priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_start()
103 writel(reg & ~WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_start()
111 writew(wdtcr, priv->base + WDTCR); in rzv2h_wdt_setup()
114 writeb(0, priv->base + WDTRCR); in rzv2h_wdt_setup()
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/linux/kernel/locking/
H A Dsemaphore.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file implements counting semaphores.
7 * A counting semaphore may be acquired 'n' times before sleeping.
8 * See mutex.c for single-acquisition sleeping locks which enforce
18 * parts of the kernel expect to be able to use down() on a semaphore in
20 * irqsave variants for down(), down_interruptible() and down_killable()
23 * The ->count variable represents how many more tasks can acquire this
48 WRITE_ONCE((sem)->last_holder, (unsigned long)current); in hung_task_sem_set_holder()
53 if (READ_ONCE((sem)->last_holder) == (unsigned long)current) in hung_task_sem_clear_if_holder()
54 WRITE_ONCE((sem)->last_holder, 0UL); in hung_task_sem_clear_if_holder()
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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h192 #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GEN…
309 #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete…
312 #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete…
315 #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete…
318 #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete…
321 #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete…
324 #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete…
444 #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt D…
447 #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt D…
450 #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt D…
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/linux/arch/alpha/include/asm/
H A Dtimex.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm-alpha/timex.h
11 the 32.768kHz reference clock, which nicely divides down to our HZ. */
18 * Only the low 32 bits are available as a continuously counting entity.
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8x60.c1 // SPDX-License-Identifier: GPL-2.0-only
14 /* De-serializer delay D/C for non-lbk mode: */ in hdmi_phy_8x60_powerup()
29 /* No matter what, start from the power down mode: */ in hdmi_phy_8x60_powerup()
56 /* Write to HIGH after PLL power down de-assert: */ in hdmi_phy_8x60_powerup()
64 * Enable the re-time logic in hdmi_phy_8x60_powerup()
88 /* If we want to use lock enable based on counting: */ in hdmi_phy_8x60_powerup()
101 /* De-assert RESET PHY from controller */ in hdmi_phy_8x60_powerdown()
113 /* Power down PHY, but keep RX-sense: */ in hdmi_phy_8x60_powerdown()
126 "core-vdda",
/linux/Documentation/devicetree/bindings/mfd/
H A Dnxp,bbnsm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Battery-Backed Non-Secure Module
10 - Jacky Bai <ping.bai@nxp.com>
13 NXP BBNSM serves as non-volatile logic and storage for the system.
15 The RTC can retain its state and continues counting even when the
16 main chip is power down. A time alarm is generated once the most
17 significant 32 bits of the real-time counter match the value in the
26 - enum:
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/linux/tools/perf/
H A Ddesign.txt3 ------------------------------
7 as instructions executed, cachemisses suffered, or branches mis-predicted -
8 without slowing down the kernel or applications. These registers can also
9 trigger interrupts when a threshold number of events have passed - and can
15 provides "virtual" 64-bit counters, regardless of the width of the
72 is divided into 3 bit-fields:
80 machine-specific.
119 will return -EINVAL.
121 More hw_event_types are supported as well, but they are CPU-specific
152 Counters come in two flavours: counting counters and sampling
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/linux/drivers/counter/
H A Drz-mtu3-cnt.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mfd/rz-mtu3.h>
31 #define RZ_MTU3_TMDR1_PH_CNT_MODE_1 (4) /* Phase counting mode 1 */
32 #define RZ_MTU3_TMDR1_PH_CNT_MODE_2 (5) /* Phase counting mode 2 */
33 #define RZ_MTU3_TMDR1_PH_CNT_MODE_3 (6) /* Phase counting mode 3 */
34 #define RZ_MTU3_TMDR1_PH_CNT_MODE_4 (7) /* Phase counting mode 4 */
35 #define RZ_MTU3_TMDR1_PH_CNT_MODE_5 (9) /* Phase counting mode 5 */
40 * 0: 16-bit, 1: 32-bit
66 * struct rz_mtu3_cnt - MTU3 counter private data
72 * @mtu_16bit_max: Cache for 16-bit counters
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/linux/drivers/platform/surface/aggregator/
H A Dcontroller.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
28 /* -- Safe counters. -------------------------------------------------------- */
31 * struct ssh_seq_counter - Safe counter for SSH sequence IDs.
39 * struct ssh_rqid_counter - Safe counter for SSH request IDs.
47 /* -- Event/notification system. -------------------------------------------- */
50 * struct ssam_nf_head - Notifier head for SSAM events.
52 * @head: List-head for notifier blocks registered under this head.
60 * struct ssam_nf - Notifier callback- and activation-registry for SSAM events.
61 * @lock: Lock guarding (de-)registration of notifier blocks. Note: This
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/linux/arch/arm/mach-imx/
H A Dsuspend-imx6.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-offsets.h>
9 #include <asm/hardware/cache-l2x0.h>
12 .arch armv7-a
38 * which defined in arch/arm/mach-imx/pm-imx6q.c, this
135 /* let DDR out of self-refresh */
158 * counting the resume address in iram
190 * put DDR explicitly into self-refresh and
197 /* make the DDR explicitly enter self-refresh. */
256 * 400us for the analog LDOs to power down.
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/linux/include/linux/pds/
H A Dpds_intr.h1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
10 * device units. Use @identity->intr_coal_mult
11 * and @identity->intr_coal_div to convert from
19 * value and begins counting down. No more
42 * @unmask -- When this bit is written with a 1
44 * @coal_timer_reset -- When this
83 #define PDS_CORE_INTR_INDEX_NOT_ASSIGNED -1
90 * enum pds_core_intr_mask_vals - valid values for mask and mask_assert.
100 * enum pds_core_intr_credits_bits - Bitwise composition of credits values.
119 iowrite32(coal, &intr_ctrl->coal_init); in pds_core_intr_coal_init()
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/linux/Documentation/core-api/
H A Dpin_user_pages.rst1 .. SPDX-License-Identifier: GPL-2.0
35 In other words, use pin_user_pages*() for DMA-pinned pages, and
45 uses a different reference counting technique.
54 flags the caller provides. The caller is required to pass in a non-null struct
62 This approach for large folios avoids the counting upper limit problems
72 --------
79 but the caller passed in a non-null struct pages* array, then the function
84 --------
89 Tracking dma-pinned pages
92 Some of the key design constraints, and solutions, for tracking dma-pinned
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/linux/arch/mips/sibyte/common/
H A Dsb_tbprof.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
7 * written by Ralf Baechle <ralf@linux-mips.org>
85 * Routines for using 40-bit SCD cycle counter
89 * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
145 u64 next = (1ULL << 40) - tb_period; in arm_tb()
156 * Unfortunately, in Pass 2 we must clear all counters to knock down in arm_tb()
166 M_SPC_CFG_ENABLE | /* enable counting */ in arm_tb()
173 M_SPC_CFG_ENABLE | /* enable counting */ in arm_tb()
182 /* XXXKW may want to expose control to the data-collector */ in arm_tb()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_types.h1 /* SPDX-License-Identifier: MIT */
54 * need to explicitly re-steer reads of registers of the other type.
56 * Only the replication types that may need additional non-default steering
69 * will always return a non-terminated value at instance (0, 0). We'll
161 * management to power down the hardware and display clocks.
192 * Accumulated time not counting the most recent block in cases
250 * Should be taken before uncore->lock in cases where both are desired.
255 * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
322 #define intel_gt_support_legacy_fencing(gt) ((gt)->ggtt->num_fences > 0)
/linux/drivers/hid/intel-ish-hid/ishtp/
H A Dishtp-dev.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 2003-2016, Intel Corporation.
13 #include <linux/intel-ish-client-if.h>
21 /* Number of messages to be held in ISR->BH FIFO */
25 * Number of IPC messages to be held in Tx FIFO, to be sent by ISR -
42 #define ISHTP_MAX_OPEN_HANDLE_COUNT (ISHTP_CLIENTS_MAX - 1)
45 #define ISHTP_HOST_CLIENT_ID_ANY (-1)
67 * struct ishtp_fw_client - representation of fw client
69 * @props - client properties
70 * @client_id - fw client id
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/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
63 -------------- | +->| GATE TIMER 0 |
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/linux/Documentation/admin-guide/thermal/
H A Dintel_powerclamp.rst6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
[all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Duncore-interconnect.json49 …"BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts th…
494 "BriefDescription": "All Writes - All Channels",
503 "BriefDescription": "Full Non-ISOCH - All Channels",
512 "BriefDescription": "Non-Inclusive - All Channels",
521 "BriefDescription": "Non-Inclusive Miss - All Channels",
530 "BriefDescription": "Partial Non-ISOCH - All Channels",
539 "BriefDescription": "DDR, acting as Cache - All Channels",
549 "BriefDescription": "DDR - All Channels",
559 "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
569 "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
[all …]
/linux/drivers/clocksource/
H A Dasm9260_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
19 #define DRIVER_NAME "asm9260-timer"
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
48 * 1 - Timer Counter and Prescale Counter are enabled for counting
49 * 0 - counters are disabled */
56 /* 00 - count up
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/linux/Documentation/hwmon/
H A Df71805f.rst44 -----------
47 capabilities. It can monitor up to 9 voltages (counting its own power
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
90 in7 VIN7 VCORE 10K - 1.00 ~1.40 V [1]_
111 --------------
113 Fan rotation speeds are reported as 12-bit values from a gated clock
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