Lines Matching +full:down +full:- +full:counting
1 // SPDX-License-Identifier: GPL-2.0
83 * The down-counter is refreshed and starts counting operation on in rzv2h_wdt_ping()
86 writeb(0x0, priv->base + WDTRR); in rzv2h_wdt_ping()
87 writeb(0xFF, priv->base + WDTRR); in rzv2h_wdt_ping()
94 u32 reg = readl(priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_stop()
96 writel(reg | WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_stop()
101 u32 reg = readl(priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_start()
103 writel(reg & ~WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_start()
111 writew(wdtcr, priv->base + WDTCR); in rzv2h_wdt_setup()
114 writeb(0, priv->base + WDTRCR); in rzv2h_wdt_setup()
117 writew(0, priv->base + WDTSR); in rzv2h_wdt_setup()
123 const struct rzv2h_of_data *of_data = priv->of_data; in rzv2h_wdt_start()
126 ret = pm_runtime_resume_and_get(wdev->parent); in rzv2h_wdt_start()
130 ret = reset_control_deassert(priv->rstc); in rzv2h_wdt_start()
132 pm_runtime_put(wdev->parent); in rzv2h_wdt_start()
136 /* delay to handle clock halt after de-assert operation */ in rzv2h_wdt_start()
141 * - CKS[7:4] - Clock Division Ratio Select in rzv2h_wdt_start()
142 * - 0101b: oscclk/256 for RZ/V2H(P) in rzv2h_wdt_start()
143 * - 1000b: pclkl/8192 for RZ/T2H in rzv2h_wdt_start()
144 * - RPSS[13:12] - Window Start Position Select - 11b: 100% in rzv2h_wdt_start()
145 * - RPES[9:8] - Window End Position Select - 11b: 0% in rzv2h_wdt_start()
146 * - TOPS[1:0] - Timeout Period Select in rzv2h_wdt_start()
147 * - 11b: 16384 cycles (3FFFh) for RZ/V2H(P) in rzv2h_wdt_start()
148 * - 01b: 4096 cycles (0FFFh) for RZ/T2H in rzv2h_wdt_start()
150 rzv2h_wdt_setup(wdev, of_data->cks_max | WDTCR_RPSS_100 | in rzv2h_wdt_start()
151 WDTCR_RPES_0 | of_data->tops); in rzv2h_wdt_start()
153 if (priv->of_data->wdtdcr) in rzv2h_wdt_start()
157 * Down counting starts after writing the sequence 00h -> FFh to the in rzv2h_wdt_start()
170 ret = reset_control_assert(priv->rstc); in rzv2h_wdt_stop()
174 if (priv->of_data->wdtdcr) in rzv2h_wdt_stop()
177 ret = pm_runtime_put(wdev->parent); in rzv2h_wdt_stop()
196 ret = clk_enable(priv->pclk); in rzv2h_wdt_restart()
200 ret = clk_enable(priv->oscclk); in rzv2h_wdt_restart()
202 clk_disable(priv->pclk); in rzv2h_wdt_restart()
206 ret = reset_control_deassert(priv->rstc); in rzv2h_wdt_restart()
208 clk_disable(priv->oscclk); in rzv2h_wdt_restart()
209 clk_disable(priv->pclk); in rzv2h_wdt_restart()
219 ret = reset_control_reset(priv->rstc); in rzv2h_wdt_restart()
224 /* delay to handle clock halt after de-assert operation */ in rzv2h_wdt_restart()
229 * - CKS[7:4] - Clock Division Ratio Select in rzv2h_wdt_restart()
230 * - 0000b: oscclk/1 for RZ/V2H(P) in rzv2h_wdt_restart()
231 * - 0100b: pclkl/4 for RZ/T2H in rzv2h_wdt_restart()
232 * - RPSS[13:12] - Window Start Position Select - 00b: 25% in rzv2h_wdt_restart()
233 * - RPES[9:8] - Window End Position Select - 00b: 75% in rzv2h_wdt_restart()
234 * - TOPS[1:0] - Timeout Period Select - 00b: 1024 cycles (03FFh) in rzv2h_wdt_restart()
236 rzv2h_wdt_setup(wdev, priv->of_data->cks_min | WDTCR_RPSS_25 | in rzv2h_wdt_restart()
239 if (priv->of_data->wdtdcr) in rzv2h_wdt_restart()
263 priv->wdtdcr = devm_platform_ioremap_resource(pdev, 1); in rzt2h_wdt_wdtdcr_init()
264 if (IS_ERR(priv->wdtdcr)) in rzt2h_wdt_wdtdcr_init()
265 return PTR_ERR(priv->wdtdcr); in rzt2h_wdt_wdtdcr_init()
267 ret = pm_runtime_resume_and_get(&pdev->dev); in rzt2h_wdt_wdtdcr_init()
273 ret = pm_runtime_put(&pdev->dev); in rzt2h_wdt_wdtdcr_init()
282 struct device *dev = &pdev->dev; in rzv2h_wdt_probe()
289 return -ENOMEM; in rzv2h_wdt_probe()
291 priv->of_data = of_device_get_match_data(dev); in rzv2h_wdt_probe()
293 priv->base = devm_platform_ioremap_resource(pdev, 0); in rzv2h_wdt_probe()
294 if (IS_ERR(priv->base)) in rzv2h_wdt_probe()
295 return PTR_ERR(priv->base); in rzv2h_wdt_probe()
297 priv->pclk = devm_clk_get_prepared(dev, "pclk"); in rzv2h_wdt_probe()
298 if (IS_ERR(priv->pclk)) in rzv2h_wdt_probe()
299 return dev_err_probe(dev, PTR_ERR(priv->pclk), "Failed to get pclk\n"); in rzv2h_wdt_probe()
301 priv->oscclk = devm_clk_get_optional_prepared(dev, "oscclk"); in rzv2h_wdt_probe()
302 if (IS_ERR(priv->oscclk)) in rzv2h_wdt_probe()
303 return dev_err_probe(dev, PTR_ERR(priv->oscclk), "Failed to get oscclk\n"); in rzv2h_wdt_probe()
305 priv->rstc = devm_reset_control_get_optional_exclusive(dev, NULL); in rzv2h_wdt_probe()
306 if (IS_ERR(priv->rstc)) in rzv2h_wdt_probe()
307 return dev_err_probe(dev, PTR_ERR(priv->rstc), in rzv2h_wdt_probe()
310 switch (priv->of_data->count_source) { in rzv2h_wdt_probe()
312 count_clk = priv->oscclk; in rzv2h_wdt_probe()
315 count_clk = priv->pclk; in rzv2h_wdt_probe()
318 return dev_err_probe(dev, -EINVAL, "Invalid count source\n"); in rzv2h_wdt_probe()
321 priv->wdev.max_hw_heartbeat_ms = (MILLI * priv->of_data->timeout_cycles * in rzv2h_wdt_probe()
322 priv->of_data->cks_div) / clk_get_rate(count_clk); in rzv2h_wdt_probe()
323 dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms); in rzv2h_wdt_probe()
329 if (priv->of_data->wdtdcr) { in rzv2h_wdt_probe()
335 priv->wdev.min_timeout = 1; in rzv2h_wdt_probe()
336 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT; in rzv2h_wdt_probe()
337 priv->wdev.info = &rzv2h_wdt_ident; in rzv2h_wdt_probe()
338 priv->wdev.ops = &rzv2h_wdt_ops; in rzv2h_wdt_probe()
339 priv->wdev.parent = dev; in rzv2h_wdt_probe()
340 watchdog_set_drvdata(&priv->wdev, priv); in rzv2h_wdt_probe()
341 watchdog_set_nowayout(&priv->wdev, nowayout); in rzv2h_wdt_probe()
342 watchdog_stop_on_unregister(&priv->wdev); in rzv2h_wdt_probe()
344 watchdog_init_timeout(&priv->wdev, 0, dev); in rzv2h_wdt_probe()
346 return devm_watchdog_register_device(dev, &priv->wdev); in rzv2h_wdt_probe()
369 { .compatible = "renesas,r9a09g057-wdt", .data = &rzv2h_wdt_of_data },
370 { .compatible = "renesas,r9a09g077-wdt", .data = &rzt2h_wdt_of_data },
383 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");