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Searched +full:dove +full:- +full:gating +full:- +full:clock (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/mvebu/
H A Ddove.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Dove SoC clocks
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 #include <linux/clk-provider.h>
18 #include "dove-divider.h"
23 * Dove PLL sample-at-reset configuration
39 * SAR0[11:9] : CPU to L2 Clock divider ratio
46 * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
157 * Clock Gating Control
185 of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock"); in dove_clk_init()
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/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "marvell,dove";
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
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/linux/drivers/pci/controller/
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
25 #include <linux/irqchip/irq-msi-lib.h>
257 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
379 writel(value, pcie->afi + offset); in afi_writel()
384 return readl(pcie->afi + offset); in afi_readl()
390 writel(value, pcie->pads + offset); in pads_writel()
395 return readl(pcie->pads + offset); in pads_readl()
430 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()
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