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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared.c1 // SPDX-License-Identifier: MIT
11 double dml2_core_shared_div_rem(double dividend, unsigned int divisor, unsigned int *remainder) in dml2_core_shared_div_rem()
13 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_shared_div_rem()
26 static void get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
44 …aceUnit(const struct dml2_display_cfg *display_cfg, bool ptoi_supported, double *PixelClockBackEnd…
56 double *BytePerPixelDETY,
57 double *BytePerPixelDETC,
69 double HRatio,
70 double HRatioChroma,
71 double VRatio,
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H A Ddml2_core_dcn4_calcs.c1 // SPDX-License-Identifier: MIT
48 static double dml2_core_div_rem(double dividend, unsigned int divisor, unsigned int *remainder) in dml2_core_div_rem()
50 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_div_rem()
58 if (!fail_only || support->ScaleRatioAndTapsSupport == 0) in dml2_print_mode_support_info()
59 dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport); in dml2_print_mode_support_info()
60 if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) in dml2_print_mode_support_info()
61 …dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndS… in dml2_print_mode_support_info()
62 if (!fail_only || support->ViewportSizeSupport == 0) in dml2_print_mode_support_info()
63 dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); in dml2_print_mode_support_info()
64 if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) in dml2_print_mode_support_info()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
182 double vtotal_avg) in optc3_fpu_set_vrr_m_const()
185 double vtotal_min, vtotal_max; in optc3_fpu_set_vrr_m_const()
186 double ratio, modulo, phase; in optc3_fpu_set_vrr_m_const()
193 * VOTAL_MAX - VTOTAL_MIN = 1 in optc3_fpu_set_vrr_m_const()
201 * of lines in a frame - 1'. in optc3_fpu_set_vrr_m_const()
213 optc->funcs->set_vtotal_min_max(optc, 0, 0); in optc3_fpu_set_vrr_m_const()
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H A Ddisplay_rq_dlg_calc_30.c42 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, in get_refcyc_per_delivery()
43 double refclk_freq_in_mhz, in get_refcyc_per_delivery()
44 double pclk_freq_in_mhz, in get_refcyc_per_delivery()
48 double vratio, in get_refcyc_per_delivery()
49 double hscale_pixel_rate, in get_refcyc_per_delivery()
53 double refcyc_per_delivery = 0.0; in get_refcyc_per_delivery()
57 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)((unsigned int)odm_combine*2) in get_refcyc_per_delivery()
58 * dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2)) in get_refcyc_per_delivery()
59 / pclk_freq_in_mhz / (double)req_per_swath_ub; in get_refcyc_per_delivery()
61 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)recout_width in get_refcyc_per_delivery()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c33 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
97 static double get_refcyc_per_delivery( in get_refcyc_per_delivery()
99 double refclk_freq_in_mhz, in get_refcyc_per_delivery()
100 double pclk_freq_in_mhz, in get_refcyc_per_delivery()
102 double vratio, in get_refcyc_per_delivery()
103 double hscale_pixel_rate, in get_refcyc_per_delivery()
107 double refcyc_per_delivery = 0.0; in get_refcyc_per_delivery()
110 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width in get_refcyc_per_delivery()
111 / pclk_freq_in_mhz / (double) req_per_swath_ub; in get_refcyc_per_delivery()
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H A Ddisplay_mode_vba.c33 * This file is gcc-parsable HW gospel, coming straight from HW engineers.
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
57 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
66 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
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H A Ddisplay_mode_structs.h68 double UrgentWatermark;
69 double WritebackUrgentWatermark;
70 double DRAMClockChangeWatermark;
71 double FCLKChangeWatermark;
72 double WritebackDRAMClockChangeWatermark;
73 double WritebackFCLKChangeWatermark;
74 double StutterExitWatermark;
75 double StutterEnterPlusExitWatermark;
76 double Z8StutterExitWatermark;
77 double Z8StutterEnterPlusExitWatermark;
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H A Ddisplay_mode_vba.h34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_…
75 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const dis…
148 double get_total_immediate_flip_bytes(
152 double get_total_immediate_flip_bw(
156 double get_total_prefetch_bw(
188 double dummy_single_array[2][DC__NUM_DPP__MAX];
190 double dummy_double_array[2][DC__NUM_DPP__MAX];
199 double HostVMInefficiencyFactor;
202 double dummy_unit_vector[DC__NUM_DPP__MAX];
203 double dummy_single[2];
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/linux/Documentation/devicetree/bindings/power/supply/
H A Dmaxim,max17040.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
18 - maxim,max17040
19 - maxim,max17041
20 - maxim,max17043
21 - maxim,max17044
22 - maxim,max17048
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/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.h1 /* SPDX-License-Identifier: MIT */
44 // Configuration of the MALL on the SoC
182 double xtalclk_mhz;
183 double dchub_refclk_mhz;
184 double dprefclk_mhz;
185 double disp_pll_vco_speed_mhz;
186 double urgent_latency_us;
187 double sr_exit_latency_us;
188 double sr_enter_plus_exit_latency_us;
189 double sr_exit_z8_time_us;
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c34 * This file is gcc-parsable HW gospel, coming straight from HW engineers.
38 * remain as-is as it provides us with a guarantee from HW that it is correct.
48 // For DML-C changes that hasn't been propagated to VBA yet
63 double DPPCLK;
64 double DISPCLK;
65 double PixelClock;
66 double DCFCLKDeepSleep;
69 double VRatio;
70 double VRatioChroma;
95 double BPP,
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c34 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
38 * remain as-is as it provides us with a guarantee from HW that it is correct.
43 double *refcyc_per_req_delivery_pre_cur,
44 double *refcyc_per_req_delivery_cur,
45 double refclk_freq_in_mhz,
46 double ref_freq_to_pix_freq,
47 double hscale_pixel_rate_l,
48 double hscl_ratio,
49 double vratio_pre_l,
50 double vratio_l,
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c34 // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
36 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
58 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
62 * remain as-is as it provides us with a guarantee from HW that it is correct.
66 double *refcyc_per_req_delivery_pre_cur,
67 double *refcyc_per_req_delivery_cur,
68 double refclk_freq_in_mhz,
69 double ref_freq_to_pix_freq,
70 double hscale_pixel_rate_l,
71 double hscl_ratio,
[all …]
H A Ddisplay_rq_dlg_calc_20v2.c34 // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
36 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
58 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
62 * remain as-is as it provides us with a guarantee from HW that it is correct.
66 double *refcyc_per_req_delivery_pre_cur,
67 double *refcyc_per_req_delivery_cur,
68 double refclk_freq_in_mhz,
69 double ref_freq_to_pix_freq,
70 double hscale_pixel_rate_l,
71 double hscl_ratio,
[all …]
H A Ddcn20_fpu.c1 // SPDX-License-Identifier: MIT
39 dc->ctx->logger
998 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
999 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context()
1001 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1 // SPDX-License-Identifier: MIT
189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
197 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()
203 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
205 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
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H A Ddisplay_mode_vba_util_32.c34 double BPP, in dml32_dscceComputeDelay()
87 p = 3 * wx - w; in dml32_dscceComputeDelay()
91 L = (ax + wx - 1) / wx; in dml32_dscceComputeDelay()
96 Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22; in dml32_dscceComputeDelay()
123 // dscc - input deserializer in dml32_dscComputeDelay()
127 // dscc - input cdc fifo in dml32_dscComputeDelay()
131 // dscc - cdc uncertainty in dml32_dscComputeDelay()
133 // dscc - output cdc fifo in dml32_dscComputeDelay()
137 // dscc - cdc uncertainty in dml32_dscComputeDelay()
139 // dscc - output serializer in dml32_dscComputeDelay()
[all …]
H A Ddisplay_mode_vba_util_32.h37 double BPP,
54 double *BytePerPixelDETY,
55 double *BytePerPixelDETC,
66 double HRatio,
67 double HRatioChroma,
68 double VRatio,
69 double VRatioChroma,
70 double MaxDCHUBToPSCLThroughput,
71 double MaxPSCLToLBThroughput,
72 double PixelClock,
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/linux/Documentation/devicetree/bindings/edac/
H A Dsocfpga-eccmgr.txt4 double bit errors which are uncorrectable.
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
24 - compatible : Should be "altr,socfpga-ocram-ecc"
25 - reg : Address and size for ECC error interrupt clear registers.
[all …]
H A Daspeed-sdram-edac.txt1 Aspeed BMC SoC EDAC node
3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
6 The memory controller supports SECDED (single bit error correction, double bit
14 - compatible: should be one of
15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
19 - interrupts: should be AVIC interrupt #0
25 compatible = "aspeed,ast2500-sdram-edac";
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c1 // SPDX-License-Identifier: MIT
16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
21 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table_fpu()
22 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
30 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_secon… in dcn401_build_wm_range_table_fpu()
32 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_… in dcn401_build_wm_range_table_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_display_cfg_types.h1 // SPDX-License-Identifier: MIT
148 dml2_twait_budgeting_setting_try, // Budget for it as long as there is an SoC state that
159 double hratio;
160 double pixel_rate_mhz;
161 double dlg_refclk_mhz;
191 double dcc_rate_plane0;
192 double dcc_rate_plane1;
193 double fraction_of_zero_size_request_plane0;
194 double fraction_of_zero_size_request_plane1;
226 double h_ratio;
[all …]
H A Ddml_top_types.h1 // SPDX-License-Identifier: MIT
144 * For example, shifting [2560, 5120, 7680] by -50 results in
165 * MCacheIDs have global scope in the SoC, and they are stored here.
289 //-----------------
291 //-----------------
345 double MaxTotalVerticalActiveAvailableBandwidth;
352 double OutputBpp[DML2_MAX_PLANES];
436 double urgent_us;
437 double writeback_urgent_us;
438 double writeback_pstate_us;
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/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra20-ehci.txt1 Tegra SOC USB controllers
4 SOC is as described in the document "Open Firmware Recommended
9 - compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
10 For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain
11 "nvidia,<chip>-ehci" plus at least one of the above, where <chip> is
13 - nvidia,phy : phandle of the PHY that the controller is connected to.
14 - clocks : Must contain one entry, for the module clock.
15 See ../clocks/clock-bindings.txt for details.
16 - resets : Must contain an entry for each entry in reset-names.
18 - reset-names : Must include the following entries:
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v12_0.h43 #define UMC_V12_0_CE_CNT_INIT (UMC_V12_0_CE_CNT_MAX - UMC_V12_0_CE_INT_THRESHOLD)
52 (UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
56 /* R13 bit shift should be considered, double the number */
61 /* column bits in SOC physical address */
65 /* row bits in SOC physical address */
69 /* channel bit in SOC physical address */
72 /* bank bit in SOC physical address */

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