| /linux/drivers/ata/ |
| H A D | sata_dwc_460ex.c | 58 u32 dmacr; /* DMA Control */ member
689 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr); in sata_dwc_clear_dmacr() local
692 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
693 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
695 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
696 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
700 * sync. If it does happen, clear dmacr anyway. in sata_dwc_clear_dmacr()
703 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n", in sata_dwc_clear_dmacr()
704 __func__, tag, hsdevp->dma_pending[tag], dmacr); in sata_dwc_clear_dmacr()
705 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, in sata_dwc_clear_dmacr()
[all …]
|
| /linux/drivers/tty/serial/ |
| H A D | amba-pl011.c | 278 unsigned int dmacr; /* dma control reg */ member
551 u16 dmacr; in pl011_dma_tx_callback() local
558 dmacr = uap->dmacr; in pl011_dma_tx_callback()
559 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
560 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
569 * get further refills (hence we check dmacr). in pl011_dma_tx_callback()
571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
660 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
661 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
695 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
[all …]
|
| /linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | fsl,imx-lcdc.yaml | 53 fsl,dmacr:
79 fsl,dmacr: false
|
| /linux/include/linux/fsl/ |
| H A D | guts.h | 106 u32 dmacr; /* 0x.0908 - DMA Control Register */ member
143 * Set the DMACR register in the GUTS
145 * The DMACR register determines the source of initiated transfers for each
160 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); in guts_set_dmacr()
|
| /linux/sound/soc/fsl/ |
| H A D | p1022_rdk.c | 41 * Set the DMACR register in the GUTS
43 * The DMACR register determines the source of initiated transfers for each
88 * Here we program the DMACR and PMUXCR registers.
166 * de-program the DMACR and PMUXCR register.
|
| H A D | p1022_ds.c | 34 * Set the DMACR register in the GUTS
36 * The DMACR register determines the source of initiated transfers for each
81 * Here we program the DMACR and PMUXCR registers.
155 * de-program the DMACR and PMUXCR register.
|
| /linux/drivers/video/fbdev/ |
| H A D | imxfb.c | 185 u_int dmacr; member
681 /* dmacr = 0 is no valid value, as we need DMA control marks. */ in imxfb_activate_var()
682 if (fbi->dmacr) in imxfb_activate_var()
683 writel(fbi->dmacr, fbi->regs + LCDC_DMACR); in imxfb_activate_var()
738 of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); in imxfb_init_fbinfo()
|
| /linux/sound/soc/rockchip/ |
| H A D | rockchip_spdif.h | 33 * DMACR
|
| H A D | rockchip_i2s.h | 128 * DMACR
|
| H A D | rockchip_sai.h | 108 /* DMACR DMA Control Register */
|
| H A D | rockchip_i2s_tdm.h | 139 * DMACR
|
| /linux/drivers/spi/ |
| H A D | spi-rockchip.c | 146 /* Bit fields in DMACR */
540 u32 dmacr = 0; in rockchip_spi_config() local
585 dmacr |= TF_DMA_EN; in rockchip_spi_config()
587 dmacr |= RF_DMA_EN; in rockchip_spi_config()
605 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); in rockchip_spi_config()
|
| H A D | spi-dw.h | 120 /* Bit fields in DMACR */
|
| H A D | spi-dw-core.c | 56 DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
|
| /linux/drivers/dma/xilinx/ |
| H A D | xilinx_dma.c | 2641 u32 dmacr; in xilinx_vdma_channel_set_config() local
2646 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()
2655 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2657 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2658 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; in xilinx_vdma_channel_set_config()
2659 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; in xilinx_vdma_channel_set_config()
2674 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; in xilinx_vdma_channel_set_config()
2675 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; in xilinx_vdma_channel_set_config()
2680 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; in xilinx_vdma_channel_set_config()
2681 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; in xilinx_vdma_channel_set_config()
[all …]
|
| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx27-apf27dev.dts | 94 fsl,dmacr = <0x00020010>;
|
| H A D | imx27-eukrea-mbimxsd27-baseboard.dts | 91 fsl,dmacr = <0x00040060>;
|
| H A D | imx25-pdk.dts | 243 fsl,dmacr = <0x00020010>;
|
| H A D | imx27-phytec-phycore-rdk.dts | 71 fsl,dmacr = <0x00020010>;
|
| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_adminq_cmd.h | 277 __le32 dmacr; member
|