| /linux/Documentation/hid/ |
| H A D | intel-thc-hid.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 - A natively half-duplex Quad I/O capable SPI master
11 - Low latency I2C interface to support HIDI2C compliant devices
12 - A HW sequencer with RW DMA capability to system memory
16 bandwidth DMA services to the touch driver and transfers the HID report to host system main memory.
18 Hardware sequencer within the THC is responsible for transferring (via DMA) data from touch devices
20 consumption (by host) in relation to data production (by touch device via DMA).
29 -------------------------------
31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully
36 ----------------------------------------------
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| /linux/drivers/scsi/ |
| H A D | zorro_esp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ESP front-end for Amiga ZORRO SCSI systems.
11 * Blizzard 1230 DMA and probe function fixes
24 * Rewritten to use 53c700.c by Kars de Jong <jongk@linux-m68k.org>
32 #include <linux/dma-mapping.h>
55 /* per-board register layout definitions */
57 /* Blizzard 1230 DMA interface */
60 unsigned char dma_addr; /* DMA address [0x0000] */
62 unsigned char dma_latch; /* DMA latch [0x8000] */
65 /* Blizzard 1230II DMA interface */
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| H A D | esp_scsi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
40 /* ESP config reg 1, read-write, found on all ESP chips */
48 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
49 #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
52 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */
55 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
58 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */
63 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
65 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
67 #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
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| /linux/drivers/staging/rtl8723bs/include/ |
| H A D | rtl8723b_spec.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
10 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
59 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
77 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
80 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
81 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
87 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
190 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
199 #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | k3dma.txt | 1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
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| H A D | intel,ldma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lightning Mountain centralized DMA controllers.
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
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| H A D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
29 - max-burst-mem-write: limit burst size for memory writes
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
51 #dma-cells = <2>;
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| /linux/include/uapi/linux/ |
| H A D | dma-buf.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 * struct dma_buf_sync - Synchronize with CPU access.
28 * When a DMA buffer is accessed from the CPU via mmap, it is not always
29 * possible to guarantee coherency between the CPU-visible map and underlying
35 * with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the
37 * DMA_BUF_SYNC_END and the same read/write flags.
45 * follow-up work is not submitted to GPU or other device driver until
50 * poll() on the DMA buffer file descriptor. If the driver or API requires
52 * other synchronization primitive outside the scope of the DMA buffer API.
65 * Indicates that the mapped DMA buffer will be read by the
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| /linux/sound/mips/ |
| H A D | hal2.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
39 /* 1=DMA Port */
40 /* 9=Global DMA Control */
46 /* If IAR_TYPE_M=DMA Port: */
53 /* If IAR_TYPE_M=Global DMA Control: */
61 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
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| /linux/Documentation/devicetree/bindings/gpu/host1x/ |
| H A D | nvidia,tegra210-nvenc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
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| H A D | nvidia,tegra210-nvdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
26 - nvidia,tegra194-nvdec
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| /linux/drivers/mtd/nand/raw/ |
| H A D | r852.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
15 byte write/read does one cycle on nand data lines.
16 dword write/read does 4 cycles
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
26 #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
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| /linux/include/linux/dma/ |
| H A D | edma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
30 * struct dw_edma_core_ops - platform-specific eDMA methods
32 * method accepts the channel id in the end-to-end
33 * numbering with the eDMA write channels being placed
56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
67 * @nr_irqs: total number of DMA IRQs
68 * @ops DMA channel to IRQ number mapping
70 * @reg_base DMA register base address
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| /linux/Documentation/PCI/ |
| H A D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 How To Write Linux PCI Drivers
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
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| /linux/drivers/comedi/drivers/ |
| H A D | plx9080.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
34 * will be transferred by the DMA engine from local or PCI memory into
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
82 /* DMA Arbitration Register (alias of MARBR). */
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
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| /linux/Documentation/devicetree/bindings/firmware/ |
| H A D | nvidia,tegra186-bpmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
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| /linux/arch/powerpc/platforms/pasemi/ |
| H A D | dma_lib.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
5 * Common functions for DMA access on PA Semi PWRficient
43 /* pasemi_read_iob_reg - read IOB register
52 /* pasemi_write_iob_reg - write IOB register
53 * @reg: Register to write to (offset into PCI CFG space)
54 * @val: Value to write
62 /* pasemi_read_mac_reg - read MAC register
72 /* pasemi_write_mac_reg - write MAC register
74 * @reg: Register to write to (offset into PCI CFG space)
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | r600_dma.c | 31 * DMA
33 * DMA engine. The programming model is very similar
35 * DMA controller has it's own packet format that is
43 * r600_dma_get_rptr - get the current read pointer
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
78 * r600_dma_set_wptr - commit the write pointer
83 * Write the wptr back to the hardware (r6xx+).
88 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
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| /linux/drivers/net/ethernet/cirrus/ |
| H A D | cs89x0.h | 1 /* Copyright, 1988-1992, Russell Nelson, Crynwr Software
13 along with this program; if not, write to the Free Software
18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
19 /* offset 2h -> Model/Product Number */
20 /* offset 3h -> Chip Revision Number */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
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| /linux/net/sunrpc/xprtrdma/ |
| H A D | svc_rdma_sendto.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (c) 2016-2018 Oracle. All rights reserved.
5 * Copyright (c) 2005-2006 Network Appliance, Inc. All rights reserved.
10 * COPYING in the main directory of this source tree, or the BSD-type
50 * The passed-in svc_rqst contains a struct xdr_buf which holds an
51 * XDR-encode
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| /linux/arch/sparc/kernel/ |
| H A D | pci_sabre.c | 1 // SPDX-License-Identifier: GPL-2.0
36 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
37 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
38 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
39 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
40 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
41 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
47 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
48 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
49 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
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| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| /linux/Documentation/arch/x86/ |
| H A D | iommu.rst | 7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
13 -----------
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
26 - IVHD - AMD I/O Virtualization Hardware Definition
33 reserved in the e820 map. When we turn on DMA translation, DMA to those
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| /linux/Documentation/driver-api/rapidio/ |
| H A D | tsi721.rst | 2 RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
9 It supports maintenance read and write operations, inbound and outbound RapidIO
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
23 - 'dbg_level'
24 - This parameter allows to control amount of debug information
32 - 'dma_desc_per_channel'
33 - This parameter defines number of hardware buffer
34 descriptors allocated for each registered Tsi721 DMA channel.
37 - 'dma_txqueue_sz'
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| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | data-fabric.json | 100 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
108 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
116 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
124 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
132 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
140 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
148 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
156 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
164 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
172 …"PublicDescription": "Write data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
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