| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | fsl-qdma.txt | 4 This device follows the generic DMA bindings defined in dma/dma.txt.
8 - compatible: Must be one of
9 "fsl,ls1021a-qdma": for LS1021A Board
10 "fsl,ls1028a-qdma": for LS1028A Board
11 "fsl,ls1043a-qdma": for ls1043A Board
12 "fsl,ls1046a-qdma": for ls1046A Board
13 - reg: Should contain the register's base address and length.
14 - interrupts: Should contain a reference to the interrupt used by this
16 - interrupt-names: Should contain interrupt names:
17 "qdma-queue0": the block0 interrupt
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| H A D | fsl-qdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
19 - fsl,ls1043a-qdma
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| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
7 Packet DMA.
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
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| H A D | k3-ringacc.txt | 5 circular data structure in memory. The RA eliminates the need for each DMA
7 state of the ring (base address, current offset). The DMA controller
14 management of the packet queues. The K3 SoCs can have more than one RA instances
17 - compatible : Must be "ti,am654-navss-ringacc";
18 - reg : Should contain register location and length of the following
20 - reg-names : should be
21 "rt" - The RA Ring Real-time Control/Status Registers
22 "fifos" - The RA Queues Registers
23 "proxy_gcfg" - The RA Proxy Global Config Registers
24 "proxy_target" - The RA Proxy Datapath Registers
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| H A D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
6 the actual data movements across clients using destination queues. Every
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
13 ------------------
15 ------------------
17 |-> DMA instance #0
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| /freebsd/share/man/man4/ |
| H A D | iflib.4 | 28 .Bl -tag -width indent
44 When set, allows the number of transmit and receive queues to be different.
45 If not set, the lower of the number of TX or RX queues will be used for both.
47 Set the number of RX queues.
48 If zero, the number of RX queues is derived from the number of cores on the
52 Set the number of TX queues.
53 If zero, the number of TX queues is derived from the number of cores on the
56 Disables MSI-X interrupts for the device.
58 Specifies a starting core offset to assign queues to.
62 Requests that RX and TX queues not be paired on the same core.
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| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
97 .Bl -diag
105 Global (across-queues) allocation failures:
106 .Bl -diag
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| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
77 Receive-side scaling (RSS) is supported for multi-core scaling.
86 Some of the ENA devices support a working mode called Low-latency
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| H A D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sa8540p-ride.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
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| H A D | sa8775p-ride.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "sa8775p-pmics.dtsi"
28 stdout-path = "serial0:115200n8";
33 regulators-0 {
34 compatible = "qcom,pmm8654au-rpmh-regulators";
35 qcom,pmic-id = "a";
38 regulator-name = "vreg_s4a";
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| /freebsd/sys/contrib/device-tree/src/arm/axis/ |
| H A D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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| /freebsd/sys/dev/neta/ |
| H A D | if_mvnetareg.h | 46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
99 /* Rx DMA Hardware Parser Registers */
117 /* Rx DMA Miscellaneous Registers */
123 /* Rx DMA Networking Controller Miscellaneous Registers */
124 #define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/
125 #define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */
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| H A D | if_mvnetavar.h | 61 bus_read_4((sc)->res[0], (reg))
63 bus_write_4((sc)->res[0], (reg), (val))
66 bus_read_region_4((sc)->res[0], (reg), (val), (c))
68 bus_write_region_4((sc)->res[0], (reg), (val), (c))
71 bus_read_4((sc)->res[0], MVNETA_PORTMIB_BASE + (reg))
76 #define MVNETA_IS_QUEUE_SET(queues, q) \ argument
77 ((((queues) >> (q)) & 0x1))
90 * DMA Descriptor
92 * the ethernet device has 8 rx/tx DMA queues. each of queue has its own
123 int dma; member
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| /freebsd/sys/contrib/device-tree/Bindings/crypto/ |
| H A D | hisilicon,hip07-sec.txt | 4 - compatible: Must contain one of
5 - "hisilicon,hip06-sec"
6 - "hisilicon,hip07-sec"
7 - reg: Memory addresses and lengths of the memory regions through which
10 Region 1 has registers for functionality common to all queues.
11 Regions 2-18 have registers for the 16 individual queues which are isolated
13 - interrupts: Interrupt specifiers.
14 Refer to interrupt-controller/interrupts.txt for generic interrupt client node
19 - dma-coherent: The driver assumes coherent dma is possible.
22 - iommus: The SEC units are behind smmu-v3 iommus.
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mp-beacon-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
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| H A D | imx8-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
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| /freebsd/sys/dev/liquidio/base/ |
| H A D | lio_droq.h | 35 * \brief Implementation of Octeon Output queues. "Output" is with
37 * view they are ingress queues.
45 * The descriptor ring is made of descriptors which have 2 64-bit values:
46 * -# Physical (bus) address of the data buffer.
47 * -# Physical (bus) address of a lio_droq_info structure.
48 * The Octeon device DMA's incoming packets and its information at the address
62 * Information about packet DMA'ed by Octeon.
131 * output/dma queue. Set to 64 assuming 1K buffers in DROQ and the fact that
138 * with non-raw opcodes.
155 /* Pointer to the OS-specific packet buffer */
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_xmit.c | 46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && in ar9300_update_tx_trig_level()
55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); in ar9300_update_tx_trig_level()
66 new_level--; in ar9300_update_tx_trig_level()
75 /* re-enable chip interrupts */ in ar9300_update_tx_trig_level()
78 AH9300(ah)->ah_tx_trig_level = new_level; in ar9300_update_tx_trig_level()
89 return (AH9300(ah)->ah_tx_trig_level); in ar9300_get_tx_trig_level()
100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; in ar9300_set_tx_queue_props()
102 if (q >= p_cap->halTotalQueues) { in ar9300_set_tx_queue_props()
106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info); in ar9300_set_tx_queue_props()
116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; in ar9300_get_tx_queue_props()
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| /freebsd/sys/contrib/dev/rtw88/ |
| H A D | pci.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
55 return skb->priority; in rtw_pci_get_tx_qsel()
61 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
64 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
68 val = bus_read_1((struct resource *)rtwpci->mmap, addr); in rtw_pci_read8()
69 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R08 (%#010x) -> %#04x\n", addr, val); in rtw_pci_read8()
76 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read16()
79 return readw(rtwpci->mmap + addr); in rtw_pci_read16()
83 val = bus_read_2((struct resource *)rtwpci->mmap, addr); in rtw_pci_read16()
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| /freebsd/sys/dev/ena/ |
| H A D | ena.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
206 ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma, in ena_dma_alloc() argument
210 device_t pdev = adapter->pdev; in ena_dma_alloc()
215 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; in ena_dma_alloc()
217 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); in ena_dma_alloc()
232 &dma->tag); in ena_dma_alloc()
238 error = bus_dma_tag_set_domain(dma->tag, domain); in ena_dma_alloc()
245 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, in ena_dma_alloc()
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| /freebsd/sys/contrib/dev/iwlwifi/ |
| H A D | iwl-prph.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
103 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
105 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
106 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
107 * but one DMA channel may take input from several queues.
109 * Tx DMA FIFOs have dedicated purposes.
112 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
114 * 0 -- EDCA BK (background) frames, lowest priority
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| /freebsd/sys/contrib/dev/iwlwifi/pcie/gen1_2/ |
| H A D | internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2003-2015, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-fh.h"
19 #include "iwl-csr.h"
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
22 #include "iwl-io.h"
23 #include "iwl-op-mode.h"
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| /freebsd/sys/dev/smartpqi/ |
| H A D | smartpqi_queue.c | 1 /*-
2 * Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
39 ob_queue_t *ob_q = &softs->admin_ob_queue; in pqisrc_submit_admin_req()
40 ib_queue_t *ib_q = &softs->admin_ib_queue; in pqisrc_submit_admin_req()
45 req->header.iu_type = in pqisrc_submit_admin_req()
47 req->header.comp_feature = 0x00; in pqisrc_submit_admin_req()
48 req->header.iu_length = PQI_STANDARD_IU_LENGTH; in pqisrc_submit_admin_req()
49 req->res1 = 0; in pqisrc_submit_admin_req()
50 req->work = 0; in pqisrc_submit_admin_req()
53 req->req_id = pqisrc_get_tag(&softs->taglist); in pqisrc_submit_admin_req()
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