Home
last modified time | relevance | path

Searched +full:dma +full:- +full:noncoherent (Results 1 – 25 of 36) sorted by relevance

12

/linux/drivers/cache/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "Cache management for noncoherent DMA"
8 These drivers implement support for noncoherent DMA master devices
H A Dstarfive_starlink_cache.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <asm/dma-noncoherent.h>
99 { .compatible = "starfive,jh8100-starlink-cache" },
111 return -ENODEV; in starlink_cache_init()
113 ret = of_property_read_u32(np, "cache-block-size", &block_size); in starlink_cache_init()
118 return -EINVAL; in starlink_cache_init()
122 return -ENOMEM; in starlink_cache_init()
H A Dax45mp_cache.c1 // SPDX-License-Identifier: GPL-2.0
3 * non-coherent cache functions for Andes AX45MP
10 #include <linux/dma-direction.h>
14 #include <asm/dma-noncoherent.h>
23 /* D-cache operation */
25 #define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
35 #define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
89 /* Write-back L1 and L2 cache entry */
115 start = start & (~(line_size - 1)); in ax45mp_dma_cache_inv()
116 end = ((end + line_size - 1) & (~(line_size - 1))); in ax45mp_dma_cache_inv()
[all …]
/linux/arch/arc/mm/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 #include <linux/dma-map-ops.h>
11 * ARCH specific callbacks for generic noncoherent DMA ops
12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
15 * For DMA coherent hardware (IOC) generic code suffices
23 * Yeah this bit us - STAR 9000898266 in arch_dma_prep_coherent()
37 * dma-mapping: provide a generic dma-noncoherent implementation)"
40 * |----------------------------------------------------------------
[all …]
/linux/arch/riscv/mm/
H A Dcache-ops.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <asm/dma-noncoherent.h>
H A Dpmem.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <asm/dma-noncoherent.h>
H A Ddma-noncoherent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
12 #include <asm/dma-noncoherent.h>
135 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", in arch_setup_dma_ops()
140 "%s %s: device non-coherent but no non-coherent operations supported", in arch_setup_dma_ops()
143 dev->dma_coherent = coherent; in arch_setup_dma_ops()
149 "Non-coherent DMA support enabled without a block size\n"); in riscv_noncoherent_supported()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
21 - one or more IRS (Interrupt Routing Service)
22 - zero or more ITS (Interrupt Translation Service)
25 - PE-Private Peripheral Interrupts (PPI)
26 - Shared Peripheral Interrupts (SPI)
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dsnps,dw-axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13 Synopsys DesignWare AXI DMA Controller DT Binding
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv1800b.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
9 #include "cv180x-cpus.dtsi"
21 interrupt-parent = <&plic>;
22 dma-noncoherent;
25 compatible = "sophgo,cv1800b-pinctrl";
28 reg-names = "sys", "rtc";
31 clk: clock-controller@3002000 {
32 compatible = "sophgo,cv1800b-clk";
35 #clock-cells = <1>;
[all …]
H A Dsg2002.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
10 #include "cv180x-cpus.dtsi"
23 interrupt-parent = <&plic>;
24 dma-noncoherent;
27 compatible = "sophgo,sg2002-pinctrl";
30 reg-names = "sys", "rtc";
33 clk: clock-controller@3002000 {
34 compatible = "sophgo,sg2002-clk", "sophgo,sg2000-clk";
[all …]
H A Dcv1812h.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
10 #include "cv180x-cpus.dtsi"
23 interrupt-parent = <&plic>;
24 dma-noncoherent;
27 compatible = "sophgo,cv1812h-pinctrl";
30 reg-names = "sys", "rtc";
33 clk: clock-controller@3002000 {
34 compatible = "sophgo,cv1812h-clk";
[all …]
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
[all …]
H A Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/pinctrl-sg2042.h>
12 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
14 #include "sg2042-cpus.dtsi"
18 #address-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmicrochip,pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
23 reg-names:
38 - description: FIC0's clock
[all …]
/linux/arch/mips/mm/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS-specific parts of the memory manager.
6 obj-y += cache.o
7 obj-y += context.o
8 obj-y += extable.o
9 obj-y += fault.o
10 obj-y += init.o
11 obj-y += mmap.o
12 obj-y += page.o
13 obj-y += page-funcs.o
[all …]
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
32 i-cache-size = <0x8000>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun55i-a523.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2 // Copyright (C) 2023-2024 Arm Ltd.
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun6i-rtc.h>
6 #include <dt-bindings/clock/sun55i-a523-ccu.h>
7 #include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
8 #include <dt-bindings/clock/sun55i-a523-r-ccu.h>
9 #include <dt-bindings/reset/sun55i-a523-ccu.h>
10 #include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
11 #include <dt-bindings/reset/sun55i-a523-r-ccu.h>
[all …]
/linux/arch/riscv/errata/thead/
H A Derrata.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/dma-noncoherent.h>
20 #include <asm/text-patching.h>
48 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
54 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
60 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
66 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
84 "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
136 /* target-c9xx cores report arch_id and impid as 0 */ in errata_probe_pmu()
153 * target-c9xx cores report arch_id and impid as 0 in errata_probe_ghostwrite()
[all …]
/linux/drivers/of/
H A Daddress.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-direct.h> /* for bus_dma_region */
58 cp = of_read_number(range + fna, na - fna); in of_bus_default_map()
60 da = of_read_number(addr + fna, na - fna); in of_bus_default_map()
66 return da - cp; in of_bus_default_map()
75 addr[na - 2] = cpu_to_be32(a >> 32); in of_bus_default_translate()
76 addr[na - in of_bus_default_translate()
[all...]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx94.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2024-2025 NXP
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx94-clock.h"
12 #include "imx94-pinfunc.h"
13 #include "imx94-power.h"
16 #address-cells = <2>;
[all …]
H A Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/clock/nxp,imx95-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx95-clock.h"
14 #include "imx95-pinfunc.h"
15 #include "imx95-power.h"
[all …]
/linux/drivers/mtd/nand/
H A Decc-realtek.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/dma-mapping.h>
16 * - BCH6 : Generate 10 ECC bytes from 512 data bytes plus 6 free bytes
17 * - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes
28 * - BBI : Bad block indicator. The first two bytes of OOB. Protected by ECC!
29 * - tag : 6 User/free bytes. First tag "contains" 2 bytes BBI. Protected by ECC!
30 * - syndrome : ECC/parity bytes
34 * +------+------+------+------+-----+------+------+------+------+-----+-----+-----+-----+
36 * +------+------+------+------+-----+------+------+------+------+-----+-----+-----+-----+
38 * +------+------+------+------+-----+------+------+------+------+-----+-----+-----+-----+
[all …]
/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
204 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"),
205 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
301 struct plda_msi *msi = &port->plda.msi; in mc_pcie_enable_msi()
316 writel_relaxed(lower_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
318 writel_relaxed(upper_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
[all …]
/linux/drivers/scsi/
H A D53c700.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
17 /* Turn on for general debugging---too verbose for normal use */
41 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
81 * for the annoying SCSI-2 requirement for LUN information in
109 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_get_sense_cmnd()
111 return hostdata->cmnd; in NCR_700_get_sense_cmnd()
117 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_set_depth()
119 hostdata->depth = depth; in NCR_700_set_depth()
124 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_get_depth()
[all …]

12