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/linux/Documentation/devicetree/bindings/dma/
H A Dnxp,lpc3220-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nxp,lpc3220-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA multiplexer for LPC32XX SoC (DMA request router)
10 - J.M.B. Downing <jonathan.downing@nautel.com>
11 - Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
14 - $ref: dma-router.yaml#
18 const: nxp,lpc3220-dmamux
23 dma-masters:
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H A Ddma-router.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Router Common Properties
10 - Vinod Koul <vkoul@kernel.org>
13 - $ref: dma-common.yaml#
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
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H A Drenesas,rzn1-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 DMA mux
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
21 description: DMA mux first register offset within the system control parent.
23 '#dma-cells':
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H A Dlpc1850-dmamux.txt1 NXP LPC18xx/43xx DMA MUX (DMA request router)
4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
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H A Dti-dma-crossbar.txt1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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/linux/Documentation/devicetree/bindings/iommu/
H A Diommu.txt13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
18 * Provide system protection against "rogue" DMA by forcing all accesses to go
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
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H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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/linux/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm3
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/linux/drivers/dma/stm32/
H A Dstm32-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
8 * DMA Router driver for STM32 DMA MUX
10 * Based on TI DMA Crossbar driver
41 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */
42 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */
44 DECLARE_BITMAP(dma_inuse, STM32_DMAMUX_MAX_DMA_REQUESTS); /* Used DMA channel */
48 u32 dma_reqs[]; /* Number of DMA Request per DMA masters.
49 * [0] holds number of DMA Masters.
70 /* Clear dma request */ in stm32_dmamux_free()
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/linux/drivers/dma/ti/
H A Ddma-crossbar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
25 .compatible = "ti,dra7-dma-crossbar",
29 .compatible = "ti,am335x-edma-crossbar",
44 u32 dma_requests; /* number of DMA requests on eDMA */
60 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
71 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
73 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
80 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
84 if (dma_spec->args_count != 3) in ti_am335x_xbar_route_allocate()
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/linux/drivers/dma/dw/
H A Drzn1-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022 Schneider-Electric
13 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
34 dev_dbg(dev, "Unmapping DMAMUX request %u\n", map->req_idx); in rzn1_dmamux_free()
36 clear_bit(map->req_idx, dmamux->used_chans); in rzn1_dmamux_free()
44 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in rzn1_dmamux_route_allocate()
51 if (dma_spec->args_count != RNZ1_DMAMUX_NCELLS) in rzn1_dmamux_route_allocate()
52 return ERR_PTR(-EINVAL); in rzn1_dmamux_route_allocate()
56 return ERR_PTR(-ENOMEM); in rzn1_dmamux_route_allocate()
58 chan = dma_spec->args[0]; in rzn1_dmamux_route_allocate()
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H A Dof.c1 // SPDX-License-Identifier: GPL-2.0
3 * Platform driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
19 struct dw_dma *dw = ofdma->of_dma_data; in dw_dma_of_xlate()
21 .dma_dev = dw->dma.dev, in dw_dma_of_xlate()
25 if (dma_spec->args_count < 3 || dma_spec->args_count > 4) in dw_dma_of_xlate()
28 slave.src_id = dma_spec->args[0]; in dw_dma_of_xlate()
29 slave.dst_id = dma_spec->args[0]; in dw_dma_of_xlate()
30 slave.m_master = dma_spec->args[1]; in dw_dma_of_xlate()
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/linux/drivers/dma/
H A Dlpc18xx-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DMA Router driver for LPC18xx/43xx DMA MUX
7 * Based on TI DMA Crossbar driver by:
8 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
48 spin_lock_irqsave(&dmamux->lock, flags); in lpc18xx_dmamux_free()
49 mux->busy = false; in lpc18xx_dmamux_free()
50 spin_unlock_irqrestore(&dmamux->lock, flags); in lpc18xx_dmamux_free()
56 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in lpc18xx_dmamux_reserve()
61 if (dma_spec->args_count != 3) { in lpc18xx_dmamux_reserve()
62 dev_err(&pdev->dev, "invalid number of dma mux args\n"); in lpc18xx_dmamux_reserve()
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H A Dlpc32xx-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Based on TI DMA Crossbar driver by:
6 // Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
38 /* From LPC32x0 User manual "3.2.1 DMA request signals" */
42 .name_sel0 = "spi2-rx-tx",
43 .name_sel1 = "ssp1-rx",
49 .name_sel0 = "uart7-rx",
50 .name_sel1 = "i2s1-dma1",
56 .name_sel0 = "spi1-rx-tx",
57 .name_sel1 = "ssp1-tx",
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/linux/drivers/staging/vme_user/
H A Dvme_fake.c1 // SPDX-License-Identifier: GPL-2.0-or-later
65 struct fake_master_window masters[FAKE_MAX_MASTER]; member
99 bridge = fake_bridge->driver_priv; in fake_VIRQ_tasklet()
101 vme_irq_handler(fake_bridge, bridge->int_level, bridge->int_statid); in fake_VIRQ_tasklet()
132 bridge = fake_bridge->driver_priv; in fake_irq_generate()
134 mutex_lock(&bridge->vme_int); in fake_irq_generate()
136 bridge->int_level = level; in fake_irq_generate()
138 bridge->int_statid = statid; in fake_irq_generate()
144 tasklet_schedule(&bridge->int_tasklet); in fake_irq_generate()
146 mutex_unlock(&bridge->vme_int); in fake_irq_generate()
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/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
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/linux/arch/arm/mach-pxa/
H A Dpxa27x.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include "addr-map.h"
7 #include "pxa2xx-regs.h"
8 #include "mfp-pxa27x.h"
13 #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
19 #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
21 #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
/linux/Documentation/i2c/
H A Ddma-considerations.rst2 Linux I2C and DMA
5 Given that I2C is a low-speed bus, over which the majority of messages
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
22 -------
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/linux/Documentation/devicetree/bindings/arm/sunxi/
H A Dallwinner,sun4i-a10-mbus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 will use to perform DMA. It also has a register interface that
17 masters on that bus.
19 Each device having to perform their DMA through the MBUS must have
20 the interconnects and interconnect-names properties set to the MBUS
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/linux/include/linux/platform_data/
H A Ddma-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Driver for the Synopsys DesignWare DMA Controller
6 * Copyright (C) 2010-2011 ST Microelectronics
22 * struct dw_dma_slave - Controller-specific information about a slave
24 * @dma_dev: required DMA master device
43 * struct dw_dma_platform_data - Controller configuration parameters
44 * @nr_masters: Number of AHB masters supported by the controller
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_common.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
11 * sizes and offsets to ensure they are 8-byte granular on types shared between
21 /* The master definition for data masters known to the firmware. */
55 * programmer (FW or META DMA). This is not a HW limitation, it is only
/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-philippe@linaro.org>
13 When virtio-iommu uses the PCI transport, its programming interface is
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
19 DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
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/linux/Documentation/devicetree/bindings/bus/
H A Dst,stm32-etzpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The ETZPC configures TrustZone security in a SoC having bus masters and
11 devices with programmable-security attributes (securable resources).
14 - Gatien Chevallier <gatien.chevallier@foss.st.com>
20 const: st,stm32-etzpc
22 - compatible
27 - const: st,stm32-etzpc
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/linux/arch/arc/boot/dts/
H A Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
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