| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | iommu.txt | 13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
18 * Provide system protection against "rogue" DMA by forcing all accesses to go
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
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| H A D | arm,smmu-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | dma-router.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
5 $schema: http://devicetree.org/meta-schema
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| H A D | snps,dw-axi-dmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13 Synopsys DesignWare AXI DMA Controller DT Binding
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
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| H A D | snps,dw-axi-dmac.txt | 1 Synopsys DesignWare AXI DMA Controller
4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - dma-channels: Number of channels supported by hardware.
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
12 - snps,priority: Priority of channel. Array size is equal to the number of
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| H A D | snps-dma.txt | 1 * Synopsys Designware DMA Controller
4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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| H A D | renesas,rzn1-dmamux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 DMA mux
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
21 description: DMA mux first register offset within the system control parent.
23 '#dma-cells':
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| H A D | st,stm32-dmamux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA MUX (DMA request router)
10 - Amelie Delaunay <amelie.delaunay@foss.st.com>
13 - $ref: dma-router.yaml#
16 "#dma-cells":
20 const: st,stm32h7-dmamux
32 - compatible
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| H A D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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| H A D | lpc1850-dmamux.txt | 1 NXP LPC18xx/43xx DMA MUX (DMA request router)
4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux value (0-3) for the peripheral
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
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| H A D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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| /freebsd/sys/contrib/device-tree/src/arm/renesas/ |
| H A D | r9a06g032.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cell
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | cci.txt | 5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | spear13xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cell
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | fsl,spdif.txt | 9 - compatible : Compatible list, should contain one of the following
11 "fsl,imx35-spdif",
12 "fsl,vf610-spdif",
13 "fsl,imx6sx-spdif",
15 - reg : Offset and length of the register set for the device.
17 - interrupts : Contains the spdif interrupt.
19 - dmas : Generic dma devicetree binding as described in
20 Documentation/devicetree/bindings/dma/dma.txt.
22 - dma-names : Two dmas have to be defined, "tx" and "rx".
24 - clocks : Contains an entry for each entry in clock-names.
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| H A D | fsl,esai.txt | 3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
10 - compatible : Compatible list, should contain one of the following
12 "fsl,imx35-esai",
13 "fsl,vf610-esai",
14 "fsl,imx6ull-esai",
15 "fsl,imx8qm-esai",
17 - reg : Offset and length of the register set for the device.
19 - interrupts : Contains the spdif interrupt.
21 - dmas : Generic dma devicetre
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| H A D | fsl,spdif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
20 - fsl,imx35-spdif
21 - fsl,vf610-spdif
22 - fsl,imx6sx-spdif
23 - fsl,imx8qm-spdif
24 - fsl,imx8qxp-spdif
25 - fsl,imx8mq-spdif
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| H A D | fsl,asrc.txt | 11 - compatible : Compatible list, should contain one of the following
13 "fsl,imx35-asrc",
14 "fsl,imx53-asrc",
15 "fsl,imx8qm-asrc",
16 "fsl,imx8qxp-asrc",
18 - reg : Offset and length of the register set for the device.
20 - interrupts : Contains the spdif interrupt.
22 - dmas : Generic dma devicetree binding as described in
23 Documentation/devicetree/bindings/dma/dma.txt.
25 - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
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| /freebsd/sys/contrib/device-tree/Bindings/virtio/ |
| H A D | iommu.txt | 3 When virtio-iommu uses the PCI transport, its programming interface is
5 device tree statically describes the relation between IOMMU and DMA
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
11 - compatible: Should be "virtio,pci-iommu"
12 - reg: PCI address of the IOMMU. As defined in the PCI Bus
13 Binding reference [1], the reg property is a five-cell
18 - #iommu-cells: Each platform DMA master managed by the IOMMU is assigned
20 For virtio-iommu, #iommu-cells must be 1.
24 - DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
25 virtio-iommu node doesn't have an "iommus" property, and is omitted from
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| H A D | mmio.txt | 3 See https://ozlabs.org/~rusty/virtio-spec/ for more details.
7 - compatible: "virtio,mmio" compatibility string
8 - reg: control registers base address and size including configuration space
9 - interrupts: interrupt generated by the device
11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
21 - iommus: If the device accesses memory through an IOMMU, it should
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| H A D | pci-iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-philippe@linaro.org>
13 When virtio-iommu uses the PCI transport, its programming interface is
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
19 DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
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| /freebsd/sys/contrib/device-tree/Bindings/arm/sunxi/ |
| H A D | allwinner,sun4i-a10-mbus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 will use to perform DMA. It also has a register interface that
17 masters on that bus.
19 Each device having to perform their DMA through the MBUS must have
20 the interconnects and interconnect-names properties set to the MBUS
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_plat_services.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
42 * - Registers read/write
43 * - Assertions
44 * - Memory barriers
45 * - Endianness conversions
95 /* *INDENT-OFF* */
99 /* *INDENT-ON* */
102 * Make sure data will be visible by other masters (other CPUS and DMA).
109 * Make sure data will be visible by DMA masters, no restriction for other cpus
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| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
77 * Generates interrupt to neighbor DMA
87 /* [0x0] Configuration of the AXI masters */
89 /* [0x4] Configuration of the AXI masters */
91 /* [0x8] Configuration of the AXI masters. Endianess configuration */
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
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| H A D | al_hal_udma_regs_s2m.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
85 * [0x0] DMA state
86 * 00 - No pending tasks
92 /* [0x4] CPU request to change DMA state */
96 * [0xc] S2M DMA error log mask.
98 * This register determines if these errors cause the S2M DMA to log the
100 * 0 - Log is enable
101 * 1 - Log is masked.
106 * [0x14] DMA header log
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