Lines Matching +full:dma +full:- +full:masters
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
22 - renesas,r9a06g032-dma
23 - const: renesas,rzn1-dma
26 "#dma-cells":
30 First cell is a phandle pointing to the DMA controller. Second one is
31 the DMA request line number. Third cell is the memory master identifier
34 cell is an optional mask of the DMA channels permitted to be allocated
46 clock-names:
50 dma-channels:
52 Number of DMA channels supported by the controller. In case if
53 not specified the driver will try to auto-detect this and
58 dma-requests:
62 dma-masters:
65 Number of DMA masters supported by the controller. In case if
66 not specified the driver will try to auto-detect this and
74 DMA channels allocation order specifier. Zero means ascending order
75 (first free allocated), while one - descending (last free allocated).
82 DMA channels priority order. Zero means ascending channels priority
90 description: Maximum block size supported by the DMA controller.
93 data-width:
94 $ref: /schemas/types.yaml#/definitions/uint32-array
95 description: Data bus width per each DMA master in bytes.
102 $ref: /schemas/types.yaml#/definitions/uint32-array
105 Data bus width per each DMA master in (2^n * 8) bits. This property is
106 deprecated. It' usage is discouraged in favor of data-width one. Moreover
107 the property incorrectly permits to define data-bus width of 8 and 16
108 bits, which is impossible in accordance with DW DMAC IP-core data book.
113 - 0 # 8 bits
114 - 1 # 16 bits
115 - 2 # 32 bits
116 - 3 # 64 bits
117 - 4 # 128 bits
118 - 5 # 256 bits
121 multi-block:
122 $ref: /schemas/types.yaml#/definitions/uint32-array
124 LLP-based multi-block transfer supported by hardware per
125 each DMA channel.
132 snps,max-burst-len:
133 $ref: /schemas/types.yaml#/definitions/uint32-array
136 This property defines the upper limit of the run-time burst setting
138 will be from 1 to max-burst-len words. It's an array property with one
147 snps,dma-protection-control:
150 Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
151 indicates the following features: bit 0 - privileged mode,
152 bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
160 - compatible
161 - "#dma-cells"
162 - reg
163 - interrupts
166 - |
167 dma-controller@fc000000 {
168 compatible = "snps,dma-spear1340";
170 interrupt-parent = <&vic1>;
173 dma-channels = <8>;
174 dma-requests = <16>;
175 dma-masters = <4>;
176 #dma-cells = <3>;
181 data-width = <8 8>;
182 multi-block = <0 0 0 0 0 0 0 0>;
183 snps,max-burst-len = <16 16 4 4 4 4 4 4>;