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/linux/drivers/mtd/nand/raw/
H A Dlpc32xx_slc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/dma-mapping.h>
30 #define LPC32XX_MODNAME "lpc32xx-nand"
56 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
57 #define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
63 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
64 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
65 #define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
66 #define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
72 #define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
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H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
185 struct mtd_oob_region ecc; member
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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H A Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
63 /* dma capabilities */
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H A Dr852.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
27 MODULE_PARM_DESC(r852_enable_dma, "Enable usage of the DMA (default)");
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
36 uint8_t reg = readb(dev->mmio + address); in r852_read_reg()
44 writeb(value, dev->mmio + address); in r852_write_reg()
51 uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); in r852_read_reg_dword()
59 writel(cpu_to_le32(value), dev->mmio + address); in r852_write_reg_dword()
70 /* check if controller supports dma */
73 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) & in r852_dma_test()
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H A Dstm32_fmc2_nand.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
28 /* ECC step size */
43 /* Max ECC buffer length */
295 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
297 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
301 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
303 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | in stm32_fmc2_nfc_timings_init()
304 FIELD_PREP(FMC2_PCR_TAR, timings->tar)); in stm32_fmc2_nfc_timings_init()
307 pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem); in stm32_fmc2_nfc_timings_init()
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H A Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
26 * - PIO - can work in master or slave DMA
27 * - CDMA - needs Master DMA for accessing command descriptors.
28 * - Generic mode - can use only slave DMA.
117 /* Size of not-last data sector. */
120 /* ECC engine configuration register 0. */
126 /* Enable controller ECC check bits generation and correction. */
129 /* ECC engine configuration register 1. */
137 /* DMA settings register. */
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H A Dlpc32xx_mlc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * - Read: Auto Decode
12 * - Write: Auto Encode
13 * - Tested Page Sizes: 2048, 4096
32 #include <linux/dma-mapping.h>
134 if (section >= nand_chip->ecc.steps) in lpc32xx_ooblayout_ecc()
135 return -ERANGE; in lpc32xx_ooblayout_ecc()
137 oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes; in lpc32xx_ooblayout_ecc()
138 oobregion->length = nand_chip->ecc.bytes; in lpc32xx_ooblayout_ecc()
148 if (section >= nand_chip->ecc.steps) in lpc32xx_ooblayout_free()
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
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H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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H A Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
10 #include <linux/dma/qcom_adm.h>
11 #include <linux/dma/qcom_bam_dma.h>
18 #include <linux/mtd/nand-qpic-common.h>
24 * by ECC (value in pages)
26 * by ECC (value in pages)
67 * protected by ECC
71 * of a page, consisting of all data, ecc, spare
74 * by ECC
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H A Dintel-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/dma-direction.h>
8 #include <linux/dma-mapping.h>
137 return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status, in ebu_nand_waitrdy()
145 u8 cs_num = ebu_host->cs_num; in ebu_nand_readb()
148 val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS); in ebu_nand_readb()
156 u8 cs_num = ebu_host->cs_num; in ebu_nand_writeb()
158 writeb(value, ebu_host->cs[cs_num].chipaddr + offset); in ebu_nand_writeb()
182 writel(0, ebu_host->ebu + EBU_CON); in ebu_nand_disable()
188 void __iomem *nand_con = ebu_host->ebu + EBU_CON; in ebu_select_chip()
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/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI EDMA DMA engine driver
9 #include <linux/dma-mapping.h>
29 #include "../virt-dma.h"
71 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
101 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
102 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
103 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
104 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
105 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
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/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
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H A Dst,stm32-fmc2-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
28 - description: tx DMA channel
29 - description: rx DMA channel
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H A Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
19 - marvell,ac5-nand-controller
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H A Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
20 - enum:
21 - ti,am64-nand
22 - ti,omap2-nand
29 - description: Interrupt for fifoevent
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H A Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
19 - allwinner,sun4i-a10-nand
20 - allwinner,sun8i-a23-nand-controller
29 - description: Bus Clock
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/linux/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qpic-snand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md sadre Alam <quic_mdalam@quicinc.com>
13 The QCOM QPIC-SPI-NAND flash controller is an extended version of
15 and parallel mode. It supports typical SPI-NAND page cache
16 operations in single, dual or quad IO mode with pipelined ECC
17 encoding/decoding using the QPIC ECC HW engine.
20 - $ref: /schemas/spi/spi-controller.yaml#
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
27 * Add Programmable Multibit ECC support for various AT91 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
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/linux/drivers/mtd/nand/
H A Decc-mtk.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * MTK ECC controller driver.
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
143 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
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H A Decc-realtek.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Realtek hardware ECC engine in RTL93xx SoCs
7 #include <linux/dma-mapping.h>
14 * The Realtek ECC engine has two operation modes.
16 * - BCH6 : Generate 10 ECC bytes from 512 data bytes plus 6 free bytes
17 * - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes
20 * are only two known devices in the wild that have NAND flash and make use of this ECC engine
25 * This driver aligns with kernel ECC naming conventions. Neverthless a short notice on the
28 * - BBI : Bad block indicator. The first two bytes of OOB. Protected by ECC!
29 * - tag : 6 User/free bytes. First tag "contains" 2 bytes BBI. Protected by ECC!
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/linux/arch/mips/dec/
H A Decc-berr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Bus error event handling code for systems equipped with ECC
20 #include <asm/cpu-type.h>
26 #include <asm/dec/ecc.h>
45 static const char dmastr[] = "DMA"; in dec_ecc_be_backend()
52 static const char eccstr[] = "ECC error"; in dec_ecc_be_backend()
65 /* For non-ECC ack ASAP, so that any subsequent errors get caught. */ in dec_ecc_be_backend()
80 /* An ECC error on a CPU or DMA transaction. */ in dec_ecc_be_backend()
84 /* A CPU timeout or a DMA overrun. */ in dec_ecc_be_backend()
90 /* For ECC errors on reads adjust for MT pipelining. */ in dec_ecc_be_backend()
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/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
26 * struct bch_geometry - BCH geometry description.
28 * @ecc_strength: A number that describes the strength of the ECC
33 * @ecc0_chunk_size: The size, in bytes, of a first ECC chunk.
34 * @eccn_chunk_size: The size, in bytes, of a single ECC chunk after
36 * @ecc_chunk_count: The number of ECC chunks in the page,
40 * the ECC status appears.
41 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
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/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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