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/linux/arch/arm/lib/
H A Dlib1funcs.S40 .macro ARM_DIV_BODY dividend, divisor, result, curbit
44 clz \curbit, \divisor
48 mov \divisor, \divisor, lsl \result
54 @ Initially shift the divisor left 3 bits if possible,
58 tst \divisor, #0xe0000000
59 moveq \divisor, \divisor, lsl #3
63 @ Unless the divisor is very big, shift it up in multiples of
65 @ division loop. Continue shifting until the divisor is
67 1: cmp \divisor, #0x10000000
68 cmplo \divisor, \dividend
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H A Ddiv64.S5 * Optimized computation of 64-bit dividend / 32-bit divisor
29 * __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
36 * r4 = divisor (preserved)
50 bls 9f @ divisor is 0 or 1
52 beq 8f @ divisor is power of 2
59 @ Align divisor with upper part of dividend.
60 @ The aligned divisor is stored in yl preserving the original.
102 @ divisor for comparisons, considering the carry-out bit as well.
139 @ divisor at this point since divisor can not be smaller than 3 here.
147 8: @ Division by a power of 2: determine what that divisor order is
/linux/arch/m68k/include/asm/
H A Dmcfpit.h25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
32 #define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */
33 #define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */
34 #define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */
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/linux/arch/alpha/lib/
H A Ddivide.S29 * the divisor is small is handled better by the DEC algorithm
38 * $1 - shifted divisor
43 * $25 - divisor
56 #define divisor $1 macro
104 bis $25,$25,divisor
109 LONGIFY(divisor)
114 beq divisor, 9f /* div by zero */
118 * shift divisor left, using 3-bit shifts for
125 1: cmpult divisor,modulus,compare
126 s8addq divisor,$31,divisor
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H A Dev6-divide.S29 * the divisor is small is handled better by the DEC algorithm
38 * $1 - shifted divisor
43 * $25 - divisor
66 #define divisor $1 macro
114 bis $25,$25,divisor # E :
120 LONGIFY(divisor) # E : U L L U
127 beq divisor, 9f /* div by zero */
137 * shift divisor left, using 3-bit shifts for
144 1: cmpult divisor,modulus,compare # E :
145 s8addq divisor,$31,divisor # E :
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/linux/tools/testing/selftests/bpf/progs/
H A Dverifier_sdiv.c15 __description("SDIV32, non-zero imm divisor, check 1")
27 __description("SDIV32, non-zero imm divisor, check 2")
39 __description("SDIV32, non-zero imm divisor, check 3")
51 __description("SDIV32, non-zero imm divisor, check 4")
63 __description("SDIV32, non-zero imm divisor, check 5")
75 __description("SDIV32, non-zero imm divisor, check 6")
87 __description("SDIV32, non-zero imm divisor, check 7")
99 __description("SDIV32, non-zero imm divisor, check 8")
111 __description("SDIV32, non-zero reg divisor, check 1")
124 __description("SDIV32, non-zero reg divisor, chec
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/linux/drivers/cpufreq/
H A Dsparc-us2e-cpufreq.c86 unsigned long old_divisor, unsigned long divisor) in frob_mem_refresh() argument
91 refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL); in frob_mem_refresh()
118 unsigned long old_divisor, unsigned long divisor) in us2e_transition() argument
123 if (old_divisor == 2 && divisor == 1) { in us2e_transition()
126 frob_mem_refresh(0, clock_tick, old_divisor, divisor); in us2e_transition()
127 } else if (old_divisor == 1 && divisor == 2) { in us2e_transition()
128 frob_mem_refresh(1, clock_tick, old_divisor, divisor); in us2e_transition()
131 } else if (old_divisor == 1 && divisor > 2) { in us2e_transition()
135 2, divisor); in us2e_transition()
136 } else if (old_divisor > 2 && divisor == 1) { in us2e_transition()
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/linux/tools/testing/selftests/tc-testing/tc-tests/filters/
H A Du32.json18 "matchPattern": "filter protocol ip pref 1 u32 chain (0[ ]+$|0 fh 800: ht divisor 1|0 fh 800::800 order 2048 key ht 800 bkt 0 flowid 1:1.*match 7f000001/ffffffff at 12)",
63 "matchPattern": "filter protocol ip pref 1 u32 chain (0[ ]+$|0 fh 800: ht divisor 1|0 fh 800::800 order 2048 key ht 800 bkt 0 flowid 1:3.*match 7f000003/ffffffff at 12)",
82 "cmdUnderTest": "$TC filter add dev $DEV1 ingress prio 99 handle 42: u32 divisor 256",
85 "matchPattern": "pref 99 u32 chain (0[ ]+$|0 fh 42: ht divisor 256|0 fh 800: ht divisor 1)",
104 "cmdUnderTest": "$TC filter replace dev $DEV1 ingress prio 99 handle 42:42 u32 divisor 256",
125 "$TC filter add dev $DEV1 ingress prio 99 handle 42: u32 divisor 256"
127 "cmdUnderTest": "$TC filter replace dev $DEV1 ingress prio 99 handle 42:42 u32 divisor 128",
130 "matchPattern": "pref 99 u32 chain (0[ ]+$|0 fh 42: ht divisor 256|0 fh 800: ht divisor
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/linux/drivers/acpi/acpica/
H A Dutmath.c243 * divisor - 32-bit divisor
257 u32 divisor, u64 *out_quotient, u32 *out_remainder) in acpi_ut_short_divide() argument
265 /* Always check for a zero divisor */ in acpi_ut_short_divide()
267 if (divisor == 0) { in acpi_ut_short_divide()
278 ACPI_DIV_64_BY_32(0, dividend_ovl.part.hi, divisor, in acpi_ut_short_divide()
281 ACPI_DIV_64_BY_32(remainder32, dividend_ovl.part.lo, divisor, in acpi_ut_short_divide()
301 * in_divisor - Divisor
316 union uint64_overlay divisor; in acpi_ut_divide() local
327 /* Always check for a zero divisor */ in acpi_ut_divide()
334 divisor.full = in_divisor; in acpi_ut_divide()
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/linux/drivers/clk/
H A Dclk-vt8500.c124 /* div == 0 is actually the highest divisor */ in vt8500_dclk_recalc_rate()
135 u32 divisor; in vt8500_dclk_determine_rate() local
140 divisor = req->best_parent_rate / req->rate; in vt8500_dclk_determine_rate()
142 /* If prate / rate would be decimal, incr the divisor */ in vt8500_dclk_determine_rate()
143 if (req->rate * divisor < req->best_parent_rate) in vt8500_dclk_determine_rate()
144 divisor++; in vt8500_dclk_determine_rate()
147 * If this is a request for SDMMC we have to adjust the divisor in vt8500_dclk_determine_rate()
150 if ((cdev->div_mask == 0x3F) && (divisor > 31)) in vt8500_dclk_determine_rate()
151 divisor = 64 * ((divisor / 64) + 1); in vt8500_dclk_determine_rate()
153 req->rate = req->best_parent_rate / divisor; in vt8500_dclk_determine_rate()
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/linux/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt41 Divisor device clocks:
44 - divisor-reg : shall be the register offset from PMC base for the divisor
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
70 divisor-reg = <0x328>;
71 divisor-mask = <0x3f>;
/linux/arch/powerpc/lib/
H A Ddiv64.S7 * the 64-bit quotient, and r4 contains the divisor.
22 divwu r7,r5,r4 # if dividend.hi >= divisor,
23 mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor
24 subf. r5,r0,r5 # dividend.hi %= divisor
31 srw r10,r10,r0 # the divisor right the same amount,
41 mulhwu r9,r11,r4 # multiply the estimate by the divisor,
42 subfc r6,r10,r6 # take the product from the divisor,
/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dsfq.json17 … "matchPattern": "qdisc sfq 1: root refcnt [0-9]+ limit 127p quantum.*depth 127 divisor 1024",
59 "matchPattern": "depth 127 divisor 1024 perturb 10sec",
80 … "matchPattern": "qdisc sfq 1: root refcnt [0-9]+ limit 127p quantum 9000b depth 127 divisor 1024",
88 "name": "Create SFQ with divisor setting",
98 "cmdUnderTest": "$TC qdisc add dev $DUMMY handle 1: root sfq divisor 512",
101 … "matchPattern": "qdisc sfq 1: root refcnt [0-9]+ limit 127p quantum 1514b depth 127 divisor 512",
143 … "matchPattern": "qdisc sfq 1: root refcnt [0-9]+ limit 127p quantum 1514b depth 64 divisor 1024",
164 …ttern": "qdisc sfq 1: root refcnt [0-9]+ limit 127p quantum 1514b depth 127 headdrop divisor 1024",
185 …sc sfq 1: root refcnt [0-9]+ limit 127p quantum 1514b depth 127 headdrop divisor 1024 ewma 6 min 8…
252 "name": "Check that a derived limit of 1 is rejected (limit 2 depth 1 divisor 1)",
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/linux/arch/xtensa/lib/
H A Dudivsi3.S12 bltui a3, 2, .Lle_one /* check if the divisor <= 1 */
16 do_nsau a4, a3, a2, a7 /* divisor_shift = nsau (divisor) */
21 sll a3, a3 /* divisor <<= count */
42 addi a2, a2, 1 /* increment quotient if dividend >= divisor */
47 beqz a3, .Lerror /* if divisor == 1, return the dividend */
51 /* return dividend >= divisor */
/linux/arch/sh/lib/
H A Dudivsi3_i4i-Os.S12 udiv small divisor: 55 cycles
13 udiv large divisor: 52 cycles
14 sdiv small divisor, positive result: 59 cycles
15 sdiv large divisor, positive result: 56 cycles
16 sdiv small divisor, negative result: 65 cycles (*)
17 sdiv large divisor, negative result: 62 cycles (*)
/linux/tools/include/uapi/linux/
H A Dconst.h54 * Divide positive or negative dividend by positive or negative divisor
57 * dividends if the divisor variable type is unsigned.
59 #define __KERNEL_DIV_ROUND_CLOSEST(x, divisor) \ argument
62 __typeof__(divisor) __d = divisor; \
65 ((__typeof__(divisor))-1) > 0 || \
/linux/lib/crypto/mpi/
H A Dmpi-div.c19 int mpi_fdiv_r(MPI rem, MPI dividend, MPI divisor) in mpi_fdiv_r() argument
21 int divisor_sign = divisor->sign; in mpi_fdiv_r()
25 /* We need the original value of the divisor after the remainder has been in mpi_fdiv_r()
29 if (rem == divisor) { in mpi_fdiv_r()
30 temp_divisor = mpi_copy(divisor); in mpi_fdiv_r()
33 divisor = temp_divisor; in mpi_fdiv_r()
36 err = mpi_tdiv_r(rem, dividend, divisor); in mpi_fdiv_r()
41 err = mpi_add(rem, rem, divisor); in mpi_fdiv_r()
113 /* Optimize division by a single-limb divisor. */ in mpi_tdiv_qr()
/linux/drivers/comedi/drivers/
H A Dcomedi_8254.c81 * Calculates the divisor value needed for a single counter to generate
85 * Calculates the two divisor values needed to the generate the pacer
89 * Transfers the intermediate divisor values to the current divisors.
93 * divisor values.
343 * @counter1: the counter number for the first divisor
344 * @counter2: the counter number for the second divisor
384 i8254->divisor = i8254->next_div & 0xffff; in comedi_8254_update_divisors()
391 * comedi_8254_cascade_ns_to_timer - calculate the cascaded divisor values
476 * comedi_8254_ns_to_timer - calculate the divisor value for nanosec timing
484 unsigned int divisor; in comedi_8254_ns_to_timer() local
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/linux/arch/m68k/lib/
H A Dudivsi3.S91 movel sp@(12), d1 /* d1 = divisor */
94 cmpl IMM (0x10000), d1 /* divisor >= 2 ^ 16 ? */
107 L3: movel d1, d2 /* use d2 as divisor backup */
108 L4: lsrl IMM (1), d1 /* shift divisor */
110 cmpl IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ? */
112 divu d1, d0 /* now we have 16 bit divisor */
113 andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
115 /* Multiply the 16 bit tentative quotient with the 32 bit divisor. Because of
/linux/arch/powerpc/boot/
H A Ddiv64.S7 * the 64-bit quotient, and r4 contains the divisor.
22 divwu r7,r5,r4 # if dividend.hi >= divisor,
23 mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor
24 subf. r5,r0,r5 # dividend.hi %= divisor
31 srw r10,r10,r0 # the divisor right the same amount,
41 mulhwu r9,r11,r4 # multiply the estimate by the divisor,
42 subfc r6,r10,r6 # take the product from the divisor,
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-jtag.c50 uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); in cvmx_helper_qlm_jtag_init() local
51 divisor = (divisor - 1) >> 2; in cvmx_helper_qlm_jtag_init()
52 /* Convert the divisor into a power of 2 shift */ in cvmx_helper_qlm_jtag_init()
53 while (divisor) { in cvmx_helper_qlm_jtag_init()
55 divisor = divisor >> 1; in cvmx_helper_qlm_jtag_init()
/linux/sound/soc/codecs/
H A Dtlv320aic26.c70 int fsref, divisor, wlen, pval, jval, dval, qval; in aic26_hw_params() local
79 case 8000: fsref = 48000; divisor = AIC26_DIV_6; break; in aic26_hw_params()
80 case 11025: fsref = 44100; divisor = AIC26_DIV_4; break; in aic26_hw_params()
81 case 12000: fsref = 48000; divisor = AIC26_DIV_4; break; in aic26_hw_params()
82 case 16000: fsref = 48000; divisor = AIC26_DIV_3; break; in aic26_hw_params()
83 case 22050: fsref = 44100; divisor = AIC26_DIV_2; break; in aic26_hw_params()
84 case 24000: fsref = 48000; divisor = AIC26_DIV_2; break; in aic26_hw_params()
85 case 32000: fsref = 48000; divisor = AIC26_DIV_1_5; break; in aic26_hw_params()
86 case 44100: fsref = 44100; divisor = AIC26_DIV_1; break; in aic26_hw_params()
87 case 48000: fsref = 48000; divisor in aic26_hw_params()
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/linux/arch/x86/kernel/
H A Dearly_printk.c96 #define DLL 0 /* Divisor Latch Low */
97 #define DLH 1 /* Divisor latch High */
134 static __init void early_serial_hw_init(unsigned divisor) in early_serial_hw_init() argument
145 static_call(serial_out)(early_serial_base, DLL, divisor & 0xff); in early_serial_hw_init()
146 static_call(serial_out)(early_serial_base, DLH, (divisor >> 8) & 0xff); in early_serial_hw_init()
159 unsigned divisor; in early_serial_init() local
192 /* Convert from baud to divisor value */ in early_serial_init()
193 divisor = 115200 / baud; in early_serial_init()
196 early_serial_hw_init(divisor); in early_serial_init()
264 unsigned divisor; in early_pci_serial_init() local
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/linux/drivers/usb/serial/
H A Dftdi_sio.h134 * For the FT232BM, a 17th divisor bit was introduced to encode the multiples
138 * 000 - add .000 to divisor
139 * 001 - add .500 to divisor
140 * 010 - add .250 to divisor
141 * 011 - add .125 to divisor
142 * 100 - add .375 to divisor
143 * 101 - add .625 to divisor
144 * 110 - add .750 to divisor
145 * 111 - add .875 to divisor
146 * Bits 15 to 0 of the 17-bit divisor are placed in the urb value. Bit 16 is
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/linux/net/sched/
H A Dsch_sfq.c110 unsigned int divisor; /* number of slots in hash table */ member
119 sfq_index *ht; /* Hash table ('divisor' slots) */
153 return skb_get_hash_perturb(skb, &q->perturbation) & (q->divisor - 1); in sfq_hash()
166 TC_H_MIN(skb->priority) <= q->divisor) in sfq_classify()
187 if (TC_H_MIN(res.classid) <= q->divisor) in sfq_classify()
642 unsigned int divisor; in sfq_change() local
654 if (ctl->divisor && in sfq_change()
655 (!is_power_of_2(ctl->divisor) || ctl->divisor > 65536)) in sfq_change()
682 divisor in sfq_change()
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