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/freebsd/sys/dev/clk/
H A Dclk_div.c66 uint32_t divider; /* in natural form */ member
82 clknode_div_table_get_divider(struct clknode_div_sc *sc, uint32_t divider) in clknode_div_table_get_divider() argument
87 return (divider); in clknode_div_table_get_divider()
89 for (table = sc->div_table; table->divider != 0; table++) in clknode_div_table_get_divider()
90 if (table->value == sc->divider) in clknode_div_table_get_divider()
91 return (table->divider); in clknode_div_table_get_divider()
97 clknode_div_table_get_value(struct clknode_div_sc *sc, uint32_t *divider) in clknode_div_table_get_value() argument
104 for (table = sc->div_table; table->divider != 0; table++) in clknode_div_table_get_value()
105 if (table->divider == *divider) { in clknode_div_table_get_value()
106 *divider = table->value; in clknode_div_table_get_value()
[all …]
H A Dclk_div.h32 #define CLK_DIV_ZERO_BASED 0x0001 /* Zero based divider. */
37 uint32_t divider; member
42 uint32_t offset; /* Divider register offset */
46 uint32_t f_width; /* set to 0 for int divider */
47 int div_flags; /* Divider-specific flags */
48 struct clk_div_table *div_table; /* Divider table */
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
152 /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */
[all …]
H A Dtegra186-clock.h362 /** @brief output of the divider IPFS_CLK_DIVISOR */
551 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
555 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
563 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
565 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
567 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
693 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
697 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
699 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
701 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
[all …]
/freebsd/sys/arm64/qoriq/clk/
H A Dls1028a_flexspi_clk.c62 { .value = 0, .divider = 1, },
63 { .value = 1, .divider = 2, },
64 { .value = 2, .divider = 3, },
65 { .value = 3, .divider = 4, },
66 { .value = 4, .divider = 5, },
67 { .value = 5, .divider = 6, },
68 { .value = 6, .divider = 7, },
69 { .value = 7, .divider = 8, },
70 { .value = 11, .divider = 12, },
71 { .value = 15, .divider = 16, },
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/freebsd/sys/contrib/device-tree/Bindings/iio/afe/
H A Dvoltage-divider.yaml4 $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml#
7 title: Voltage divider
13 When an io-channel measures the midpoint of a voltage divider, the
15 of the divider. This binding describes the voltage divider in such
35 const: voltage-divider
45 output channel, the voltage divider can act as a provider of
48 such as a voltage divider, and then consuming its raw value
49 isn't interesting. In this case, the voltage before the divider
59 Resistance R + Rout for the full divider. The io-channel is scaled by
75 * voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
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H A Dvoltage-divider.txt1 Voltage divider
4 When an io-channel measures the midpoint of a voltage divider, the
6 of the divider. This binding describes the voltage divider in such
24 - compatible : "voltage-divider"
28 - full-ohms : Resistance R + Rout for the full divider. The io-channel
33 voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
36 compatible = "voltage-divider";
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddivider.txt1 Binding for TI divider clock
4 register-mapped adjustable clock rate divider that does not gate and has
42 The binding must also provide the register to control the divider and
43 unless the divider array is provided, min and max dividers. Optionally
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - reg : offset for register controlling adjustable divider
62 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
76 - ti,latch-bit : latch the divider value to HW, only needed if the register
77 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
83 compatible = "ti,divider-clock";
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
H A Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
27 reg-names = "control", "multiplier", "post-divider";
64 - compatible : shall be "ti,keystone,pll-divider-clock"
68 - bit-mask : arbitrary bitmask for programming the divider
76 compatible = "ti,keystone,pll-divider-clock";
H A Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
H A Ddove-divider-clock.txt1 PLL divider based Dove clocks
17 - compatible : shall be "marvell,dove-divider-clock"
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
25 compatible = "marvell,dove-divider-clock";
/freebsd/sys/arm/mv/clk/
H A Da37x0_nb_periph_clk_driver.c50 { .value = 1, .divider = 1 },
51 { .value = 2, .divider = 2 },
52 { .value = 3, .divider = 3 },
53 { .value = 4, .divider = 4 },
54 { .value = 5, .divider = 5 },
55 { .value = 6, .divider = 6 },
56 { .value = 0, .divider = 0 }
60 { .value = 0, .divider = 1 },
61 { .value = 1, .divider = 2 },
62 { .value = 2, .divider = 4 },
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dltc3676.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <127000 200000>;
48 lltc,fb-voltage-divider = <301000 200000>;
57 lltc,fb-voltage-divider = <127000 200000>;
66 lltc,fb-voltage-divider = <221000 200000>;
75 lltc,fb-voltage-divider = <487000 200000>;
89 lltc,fb-voltage-divider = <634000 200000>;
H A Dltc3589.txt17 - lltc,fb-voltage-divider: An array of two integers containing the resistor
18 values R1 and R2 of the feedback voltage divider in ohms.
39 lltc,fb-voltage-divider = <100000 158000>;
48 lltc,fb-voltage-divider = <180000 191000>;
57 lltc,fb-voltage-divider = <270000 100000>;
66 lltc,fb-voltage-divider = <511000 158000>;
74 lltc,fb-voltage-divider = <100000 158000>;
82 lltc,fb-voltage-divider = <180000 191000>;
H A Dmps,mp886x.yaml28 mps,fb-voltage-divider:
30 values R1 and R2 of the feedback voltage divider in kilo ohms.
42 - mps,fb-voltage-divider
58 mps,fb-voltage-divider = <80 240>;
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap54xx-clocks.dtsi134 compatible = "ti,divider-clock";
153 compatible = "ti,divider-clock";
163 compatible = "ti,divider-clock";
182 compatible = "ti,divider-clock";
216 compatible = "ti,divider-clock";
244 compatible = "ti,divider-clock";
254 compatible = "ti,divider-clock";
264 compatible = "ti,divider-clock";
274 compatible = "ti,divider-clock";
284 compatible = "ti,divider-clock";
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H A Domap44xx-clocks.dtsi170 compatible = "ti,divider-clock";
191 compatible = "ti,divider-clock";
202 compatible = "ti,divider-clock";
238 compatible = "ti,divider-clock";
250 compatible = "ti,divider-clock";
271 compatible = "ti,divider-clock";
283 compatible = "ti,divider-clock";
292 compatible = "ti,divider-clock";
302 compatible = "ti,divider-clock";
312 compatible = "ti,divider-clock";
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H A Ddra7xx-clocks.dtsi244 compatible = "ti,divider-clock";
256 compatible = "ti,divider-clock";
266 compatible = "ti,divider-clock";
278 compatible = "ti,divider-clock";
322 compatible = "ti,divider-clock";
351 compatible = "ti,divider-clock";
408 compatible = "ti,divider-clock";
458 compatible = "ti,divider-clock";
508 compatible = "ti,divider-clock";
522 compatible = "ti,divider-clock";
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H A Ddm816x-clocks.dtsi95 compatible = "ti,divider-clock";
113 compatible = "ti,divider-clock";
121 compatible = "ti,divider-clock";
129 compatible = "ti,divider-clock";
137 compatible = "ti,divider-clock";
145 compatible = "ti,divider-clock";
153 compatible = "ti,divider-clock";
161 compatible = "ti,divider-clock";
169 compatible = "ti,divider-clock";
185 compatible = "ti,divider-clock";
/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt21 - adi,reference-div2-enable: Enables reference divider.
36 4: N-Divider output
48 - adi,12bit-clk-divider: Clock divider value used when
50 - adi,clk-divider-mode:
52 0: Clock divider off (default)
H A Dadi,adf4350.yaml63 description: Enables reference divider.
93 4: N-Divider output
119 adi,12bit-clk-divider:
122 Clock divider value used when adi,12bit-clkdiv-mode != 0
124 adi,clk-divider-mode:
129 0: Clock divider off (default)
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dmaxim,max20730.yaml36 vout-voltage-divider:
38 If voltage divider present at vout, the voltage at voltage sensor pin
40 meaningful number if voltage divider present. It has two numbers,
63 vout-voltage-divider = <1000 2000>; // vout would be scaled to 0.5
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dmpc5xxx-mscan.txt21 also specify which clock source and divider shall be used for the controller:
32 - fsl,mscan-clock-divider: for the reference and system clock, an additional
33 clock divider can be specified. By default, a
52 fsl,mscan-clock-divider = <3>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx53-usbarmory.dts153 lltc,fb-voltage-divider = <100000 158000>;
162 lltc,fb-voltage-divider = <180000 191000>;
171 lltc,fb-voltage-divider = <270000 100000>;
180 lltc,fb-voltage-divider = <511000 158000>;
188 lltc,fb-voltage-divider = <100000 158000>;
196 lltc,fb-voltage-divider = <180000 191000>;

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