divider\-shift (full) in projects: linux

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Searched +full:divider +full:- +full:shift (Results 1 – 25 of 220) sorted by relevance

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/linux/drivers/clk/tegra/
H A D	clk-divider.c	1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <linux/clk-provider.h> 14 #define pll_out_override(p) (BIT((p->shift - 6))) 15 #define div_mask(d) ((1 << (d->width)) - 1) 16 #define get_mul(d) (1 << d->frac_width) 21 static int get_div(struct tegra_clk_frac_div divider, unsigned long rate, in get_div() argument 26 div = div_frac_get(rate, parent_rate, divider->width, in get_div() 27 divider->frac_width, divider->flags); in get_div() 38 struct tegra_clk_frac_div divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local 43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate() [all …]
/linux/drivers/clk/
H A D	clk-divider.c	1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 7 * Adjustable divider clock implementation 10 #include <linux/clk-provider.h> 20 * DOC: basic adjustable divider clock that cannot gate 23 * prepare - clk_prepare only ensures that parents are prepared 24 * enable - clk_enable only ensures that parents are enabled 25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 26 * parent - fixed parent. No clk_set_parent support 29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument [all …]
H A D	clk-milbeaut.c	`1 // SPDX-License-Identifier: GPL-2.0 7 #include <linux/clk-provider.h> 17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) 20 #define M10V_PLL1DIV2 "pll1-2" 22 #define M10V_PLL2DIV2 "pll2-2" 24 #define M10V_PLL6DIV2 "pll6-2" 25 #define M10V_PLL6DIV3 "pll6-3" 27 #define M10V_PLL7DIV2 "pll7-2" 28 #define M10V_PLL7DIV5 "pll7-5" 31 #define M10V_PLL10DIV2 "pll10-2" [all …]`
/linux/drivers/clk/imx/
H A D	clk-divider-gate.c	1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <linux/clk-provider.h> 15 struct clk_divider divider; member 23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate() 32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro() 33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro() 37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro() 38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro() 49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate() 52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate() [all …]
/linux/drivers/clk/qcom/
H A D	clk-regmap-divider.c	1 // SPDX-License-Identifier: GPL-2.0-only 11 #include "clk-regmap-divider.h" 21 struct clk_regmap_div divider = to_clk_regmap_div(hw); in div_round_ro_rate() local 22 struct clk_regmap clkr = &divider->clkr; in div_round_ro_rate() 25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate() 26 val >>= divider->shift; in div_round_ro_rate() 27 val &= BIT(divider->width) - 1; in div_round_ro_rate() 29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate() 36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local 38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate() [all …]
/linux/drivers/clk/hisilicon/
H A D	clkdivider-hi6220.c	`1 // SPDX-License-Identifier: GPL-2.0-only 3 * Hisilicon hi6220 SoC divider clock driver 11 #include <linux/clk-provider.h> 19 #define div_mask(width) ((1 << (width)) - 1) 22 * struct hi6220_clk_divider - divider clock for hi6220 24 * @hw: handle between common and hardware-specific interfaces 25 * @reg: register containing divider 26 * @shift: shift to the divider bit field 27 * @width: width of the divider bit field 28 * @mask: mask for setting divider rate [all …]`
/linux/drivers/clk/rockchip/
H A D	clk-half-divider.c	1 // SPDX-License-Identifier: GPL-2.0 6 #include <linux/clk-provider.h> 11 #define div_mask(width) ((1 << (width)) - 1) 17 return abs(rate - now) < abs(rate - best); in _is_best_half_div() 25 struct clk_divider divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local 28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate() 29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate() 54 bestdiv = (bestdiv - 3) / 2; in clk_half_divider_bestdiv() 60 The maximum divider we can use without overflowing in clk_half_divider_bestdiv() 70 * parent rate, so return the divider immediately. in clk_half_divider_bestdiv() [all …]
/linux/include/linux/
H A D	clk-provider.h	1 /* SPDX-License-Identifier: GPL-2.0 / 3 Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 14 * top-level framework. custom flags for dealing with hardware specifics 20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent / 26 #define CLK_SET_RATE_NO_REPARENT BIT(7) / don't re-parent on rate change / 31 / parents need enable during gate/ungate, set rate and re-parent / 42 struct clk_rate_request - Structur 716 u8 shift; global() member 791 clk_register_divider(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,lock) global() argument 808 clk_hw_register_divider(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,lock) global() argument 827 clk_hw_register_divider_parent_hw(dev,name,parent_hw,flags,reg,shift,width,clk_divider_flags,lock) global() argument 846 clk_hw_register_divider_parent_data(dev,name,parent_data,flags,reg,shift,width,clk_divider_flags,lock) global() argument 866 clk_hw_register_divider_table(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 886 clk_hw_register_divider_table_parent_hw(dev,name,parent_hw,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 907 clk_hw_register_divider_table_parent_data(dev,name,parent_data,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 926 devm_clk_hw_register_divider(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,lock) global() argument 944 devm_clk_hw_register_divider_parent_hw(dev,name,parent_hw,flags,reg,shift,width,clk_divider_flags,lock) global() argument 965 devm_clk_hw_register_divider_table(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 1009 u8 shift; global() member 1046 clk_register_mux(dev,name,parent_names,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1051 clk_hw_register_mux_table(dev,name,parent_names,num_parents,flags,reg,shift,mask,clk_mux_flags,table,lock) global() argument 1058 clk_hw_register_mux_table_parent_data(dev,name,parent_data,num_parents,flags,reg,shift,mask,clk_mux_flags,table,lock) global() argument 1065 clk_hw_register_mux(dev,name,parent_names,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1071 clk_hw_register_mux_hws(dev,name,parent_hws,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1076 clk_hw_register_mux_parent_data(dev,name,parent_data,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1082 clk_hw_register_mux_parent_data_table(dev,name,parent_data,num_parents,flags,reg,shift,width,clk_mux_flags,table,lock) global() argument 1089 devm_clk_hw_register_mux(dev,name,parent_names,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1095 devm_clk_hw_register_mux_parent_hws(dev,name,parent_hws,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1102 devm_clk_hw_register_mux_parent_data_table(dev,name,parent_data,num_parents,flags,reg,shift,width,clk_mux_flags,table,lock) global() argument 1274 u8 shift; global() member [all...]
/linux/Documentation/devicetree/bindings/clock/
H A D	keystone-pll.txt	2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL 9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 12 - #clock-cells : from common clock binding; shall be set to 0. 13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" 14 - clocks : parent clock phandle 15 - reg - pll control0 and pll multiplier registers 16 - reg-names : control, multiplier and post-divider. The multiplier and 17 post-divider registers are applicable only for main pll clock 18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits 23 #clock-cells = <0>; [all …]
/linux/drivers/clk/x86/
H A D	clk-cgu.c	1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2020-2022 MaxLinear, Inc. 8 #include <linux/clk-provider.h> 12 #include "clk-cgu.h" 29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed() 30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed() 31 list->div_width, list->div_val); in lgm_clk_register_fixed() 33 return clk_hw_register_fixed_rate(NULL, list->name, in lgm_clk_register_fixed() 34 list->parent_data[0].name, in lgm_clk_register_fixed() 35 list->flags, list->mux_flags); in lgm_clk_register_fixed() [all …]
/linux/arch/arm/boot/dts/ti/omap/
H A D	omap44xx-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "extalt_clkin_ck"; 12 clock-frequency = <59000000>; 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 clock-output-names = "pad_clks_src_ck"; 19 clock-frequency = <12000000>; 23 #clock-cells = <0>; [all …]`
H A D	omap54xx-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "pad_clks_src_ck"; 12 clock-frequency = <12000000>; 16 #clock-cells = <0>; 17 compatible = "ti,gate-clock"; 18 clock-output-names = "pad_clks_ck"; 20 ti,bit-shift = <8>; 25 #clock-cells = <0>; [all …]`
H A D	am43xx-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 8 sys_clkin_ck: clock-sys-clkin-31@40 { 9 #clock-cells = <0>; 10 compatible = "ti,mux-clock"; 11 clock-output-names = "sys_clkin_ck"; 13 ti,bit-shift = <31>; 17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { 18 #clock-cells = <0>; 19 compatible = "ti,mux-clock"; 20 clock-output-names = "crystal_freq_sel_ck"; [all …]`
H A D	omap24xx-clocks.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 9 #clock-cells = <0>; 10 compatible = "ti,composite-mux-clock"; 12 ti,bit-shift = <2>; 17 #clock-cells = <0>; 18 compatible = "ti,composite-clock"; 23 #clock-cells = <0>; 24 compatible = "ti,composite-mux-clock"; 26 ti,bit-shift = <6>; 31 #clock-cells = <0>; [all …]`
/linux/drivers/clk/ti/
H A D	divider.c	`1 // SPDX-License-Identifier: GPL-2.0-only 3 * TI Divider Clock 7 * Tero Kristo <t-kristo@ti.com> 10 #include <linux/clk-provider.h> 26 for (clkt = table; clkt->div; clkt++) in _get_table_div() 27 if (clkt->val == val) in _get_table_div() 28 return clkt->div; in _get_table_div() 32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument 38 if (divider->table) { in _setup_mask() 41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask() [all …]`
/linux/drivers/clk/mxs/
H A D	clk-frac.c	`1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <linux/clk-provider.h> 13 * struct clk_frac - mxs fractional divider clock 14 * @hw: clk_hw for the fractional divider clock 16 * @shift: the divider bit shift 17 * @width: the divider bit width 18 * @busy: busy bit shift 20 * The clock is an adjustable fractional divider with a busy bit to wait 21 * when the divider is adjusted. 26 u8 shift; member [all …]`
/linux/drivers/clk/keystone/
H A D	pll.c	`1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Murali Karicheri <m-karicheri2@ti.com> 9 #include <linux/clk-provider.h> 26 * struct clk_pll_data - pll data structure 28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6) 36 * @pllod: PLL register map address for post divider bits 40 * @pllm_upper_shift: multiplier upper shift 41 * @plld_mask: divider mask 42 * @clkod_mask: output divider mask 43 * @clkod_shift: output divider shift [all …]`
/linux/drivers/clk/stm32/
H A D	clk-stm32-core.c	1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 17 #include "clk-stm32-core.h" 18 #include "reset-stm32.h" 26 const struct stm32_rcc_match_data data = match->data; in stm32_rcc_clock_init() 27 struct clk_hw_onecell_data clk_data = data->hw_clks; in stm32_rcc_clock_init() 31 max_binding = data->maxbinding; in stm32_rcc_clock_init() 35 return -ENOMEM; in stm32_rcc_clock_init() 37 clk_data->num = max_binding; in stm32_rcc_clock_init() 39 hws = clk_data->hws; in stm32_rcc_clock_init() [all …]
/linux/drivers/clk/bcm/
H A D	clk-kona.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 16 #include <linux/clk-provider.h> 24 #define BAD_CLK_NAME ((const char )-1) 33 #define FLAG_SET(obj, type, flag) ((obj)->flags \|= FLAG(type, flag)) 34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) 35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) 36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) 40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0) 44 #define policy_exists(policy) ((policy)->offset != 0) 55 #define hyst_exists(hyst) ((hyst)->offset != 0) [all …]
H A D	clk-kona.c	1 // SPDX-License-Identifier: GPL-2.0-only 7 #include "clk-kona.h" 12 #include <linux/clk-provider.h> 28 /* Produces a mask of set bits covering a range of a 32-bit value */ 29 static inline u32 bitfield_mask(u32 shift, u32 width) in bitfield_mask() argument 31 return ((1 << width) - 1) << shift; in bitfield_mask() 35 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument 37 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract() 41 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) in bitfield_replace() argument 43 u32 mask = bitfield_mask(shift, width); in bitfield_replace() [all …]
/linux/drivers/clk/sprd/
H A D	div.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 3 // Spreadtrum divider clock driver 14 struct sprd_div_internal - Internal divider description 15 * @shift: Bit offset of the divider in its register 16 * @width: Width of the divider field in its register 18 * That structure represents a single divider, and is meant to be 24 u8 shift; member 31 .shift = _shift, \`
/linux/drivers/clk/sunxi-ng/
H A D	ccu_div.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 9 #include <linux/clk-provider.h> 15 struct ccu_div_internal - Internal divider description 16 * @shift: Bit offset of the divider in its register 17 * @width: Width of the divider field in its register 18 * @max: Maximum value allowed for that divider. This is the 21 * @flags: clk_divider flags to apply on this divider 22 * @table: Divider table pointer (if applicable) 24 * That structure represents a single divider, and is meant to be 32 u8 shift; member [all …]
H A D	ccu_phase.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 #include <linux/clk-provider.h> 22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase() 23 delay = (reg >> phase->shift); in ccu_phase_get_phase() 24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase() 32 return -EINVAL; in ccu_phase_get_phase() 37 return -EINVAL; in ccu_phase_get_phase() 42 return -EINVAL; in ccu_phase_get_phase() 47 return -EINVAL; in ccu_phase_get_phase() [all …]
/linux/drivers/clk/sunxi/
H A D	clk-sunxi.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 9 #include <linux/clk-provider.h> 14 #include <linux/reset-controller.h> 19 #include "clk-factors.h" 27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 38 div = req->rate / 6000000; in sun4i_get_pll1_factors() 39 req->rate = 6000000 * div; in sun4i_get_pll1_factors() 42 req->m = 0; in sun4i_get_pll1_factors() 45 if (req->rate >= 768000000 \|\| req->rate == 42000000 \|\| in sun4i_get_pll1_factors() 46 req->rate == 54000000) in sun4i_get_pll1_factors() [all …]
/linux/drivers/mfd/
H A D	sm501.c	1 // SPDX-License-Identifier: GPL-2.0-only 19 #include <linux/platform_data/i2c-gpio.h> 25 #include <linux/sm501-regs.h> 135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); in sm501_dump_clk() 136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); in sm501_dump_clk() 137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); in sm501_dump_clk() 138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); in sm501_dump_clk() 163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", in sm501_dump_clk() 166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", in sm501_dump_clk() 169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); in sm501_dump_clk() [all …]

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