Home
last modified time | relevance | path

Searched +full:divider +full:- +full:clock (Results 1 – 25 of 280) sorted by relevance

12345678910>>...12

/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9 * @defgroup bpmp_clock_ids Clock ID's
36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
52 * divided by the divider controlled by ACLK_CLK_DIVISOR in
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
58 /** @brief clock recovered from EAVB input */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
[all …]
H A Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * @defgroup clock_ids Clock Identifiers
235 * @defgroup nafll_clks NAFLL clock sources
355 * pwrclk. @warning: This is almost certainly not the clock you think
356 * it is. If you're looking for the clock of the graphics engine, see
362 /** @brief output of the divider IPFS_CLK_DIVISOR */
417 * @brief controls the EMC clock frequency.
418 * @details Doing a clk_set_rate on this clock will select the
419 * appropriate clock source, program the source rate and execute a
420 * specific sequence to switch to the new clock source for both memory
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
H A Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
7 This binding uses the common clock binding[1].
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
[all …]
H A Ddove-divider-clock.txt1 PLL divider based Dove clocks
9 ID Clock
10 -------------
11 0 AXI bus clock
12 1 GPU clock
13 2 VMeta clock
14 3 LCD clock
17 - compatible : shall be "marvell,dove-divider-clock"
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
[all …]
H A Dapm,xgene-device-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC device clocks
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-device-clock
20 reg-names:
22 - enum: [ csr-reg, div-reg ]
23 - const: div-reg
[all …]
H A Dnspire-clock.txt1 TI-NSPIRE Clocks
4 - compatible: Valid compatible properties include:
5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
7 "lsi,nspire-cx-clock" for the base clock in the CX model
8 "lsi,nspire-classic-clock" for the base clock in the older model
10 - reg: Physical base address of the controller and length of memory mapped
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
15 clock where it divides the rate from.
20 #clock-cells = <0>;
[all …]
H A Dmarvell,dove-divider-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/marvell,dove-divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Dove PLL Divider Clock
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
20 ID Clock
21 -------------
22 0 AXI bus clock
[all …]
H A Dsilabs,si5351.txt1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
[all …]
H A Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddivider.txt1 Binding for TI divider clock
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped adjustable clock rate divider that does not gate and has
5 only one input clock or parent. By default the value programmed into
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
42 The binding must also provide the register to control the divider and
43 unless the divider array is provided, min and max dividers. Optionally
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
H A Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments divider clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
14 that does not gate and has only one input clock or parent. By default the
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
[all …]
H A Dcomposite.txt1 Binding for TI composite clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped composite clock with multiple different sub-types;
6 a multiplexer clock with multiple input clock signals or parents, one
9 an adjustable clock rate divider, this behaves exactly as [3]
12 clock, this behaves exactly as [4]
15 merged to this clock. The component clocks shall be of one of the
16 "ti,*composite*-clock" types.
18 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 [2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
[all …]
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for DRA7xx clock data
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
[all …]
H A Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
[all …]
/freebsd/sys/arm64/qoriq/clk/
H A Dls1028a_flexspi_clk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
62 { .value = 0, .divider = 1, },
63 { .value = 1, .divider = 2, },
64 { .value = 2, .divider = 3, },
65 { .value = 3, .divider = 4, },
66 { .value = 4, .divider = 5, },
67 { .value = 5, .divider = 6, },
68 { .value = 6, .divider = 7, },
69 { .value = 7, .divider = 8, },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
10 ADF435x Reference Clock (CLKIN).
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
[all …]
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
26 description: Clock to provide CLKIN reference clock signal.
28 clock-names:
31 '#clock-cells':
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dmpc5xxx-mscan.txt2 ------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
7 fsl,mpc5200-mscan nodes
8 -----------------------
9 In addition to the required compatible-, reg- and interrupt-properties, you can
10 also specify which clock source shall be used for the controller:
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bus clock
14 "ref" for reference clock (XTAL)
18 fsl,mpc5121-mscan nodes
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dmediatek,mt8188-afe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8188-af
[all...]
H A Dmt8186-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
14 const: mediatek,mt8186-sound
25 reset-names:
28 memory-region:
46 - description: audio infra sys clock
47 - description: audio infra 26M clock
[all …]
H A Dmt8195-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-af
[all...]

12345678910>>...12