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/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Ddisplay-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/display-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: display timings
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
12 - Sam Ravnborg <sam@ravnborg.org>
15 A display panel may be able to handle several display timings,
17 The display-timings node makes it possible to specify the timings
[all …]
H A Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Display Panel
[all...]
H A Dsamsung,s6e8aa0.txt4 - compatible: "samsung,s6e8aa0"
5 - reg: the virtual channel number of a DSI peripheral
6 - vdd3-supply: core voltage supply
7 - vci-supply: voltage supply for analog circuits
8 - reset-gpios: a GPIO spec for the reset pin
9 - display-timings: timings for the connected panel as described by [1]
12 - power-on-delay: delay after turning regulators on [ms]
13 - reset-delay: delay after reset sequence [ms]
14 - init-delay: delay after initialization sequence [ms]
15 - panel-width-mm: physical panel width [mm]
[all …]
H A Dsamsung,s6e8aa0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/samsung,s6e8aa0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
[all …]
H A Dsamsung,ld9040.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/samsung,ld9040.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
20 display-timings: true
23 reset-gpios: true
25 vdd3-supply:
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H A Dpanel-edp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
17 board, either for second-sourcing purposes or to support multiple SKUs
23 the panel. We can use this to identify display size, resolution, and
24 timings among other things.
27 provided anywhere on the DP AUX bus is the power sequencing timings.
[all …]
H A Dpanel-dsi-cm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/pane
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H A Ddisplay-timing.txt1 See display-timings.yaml in this directory.
/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
14 multiplexer in the front to select any of the four IPU display
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
[all …]
H A Dfsl,imx-fb.txt6 - compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
7 - reg : Should contain 1 register ranges(address and length)
8 - interrupts : One interrupt of the fb dev
11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
13 Additional, the display node has to define properties:
14 - bits-per-pixel: Bits per pixel
15 - fsl,pcr: LCDC PCR value
16 A display node may optionally define
17 - fsl,aus-mode: boolean to enable AUS mode (only for imx21)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos7-decon.txt1 Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
3 DECON (Display and Enhancement Controller) is the Display Controller for the
8 - compatible: value should be "samsung,exynos7-decon";
10 - reg: physical base address and length of the DECON registers set.
12 - interrupts: should contain a list of all DECON IP block interrupts in the
16 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
20 - pinctrl-0: pin control group to be used for this controller.
22 - pinctrl-names: must contain a "default" entry.
24 - clocks: must include clock specifiers corresponding to entries in the
25 clock-names property.
[all …]
H A Dsamsung-fimd.txt1 Device-Tree bindings for Samsung SoC display controller (FIMD)
3 FIMD (Fully Interactive Mobile Display) is the Display Controller for the
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
15 "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
[all …]
H A Dexynos_dp.txt1 The Exynos display port interface should be configured based on
5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,exynos7-decon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
16 DECON (Display and Enhancement Controller) is the Display Controller for the
[all …]
H A Dsamsung,fimd.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,s3c2443-fimd
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tilcdc/
H A Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dwm,wm8505-fb.txt2 -----------------------------------------------------
5 - compatible : "wm,wm8505-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - bits-per-pixel : bit depth of framebuffer (16 or 32)
10 - display-timings: see display-timing.txt for information
15 compatible = "wm,wm8505-fb";
17 bits-per-pixel = <16>;
19 display-timings {
20 native-mode = <&timing0>;
22 clock-frequency = <0>; /* unused but required */
[all …]
H A Dvia,vt8500-fb.txt2 -----------------------------------------------------
5 - compatible : "via,vt8500-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - interrupts : framebuffer controller interrupt
8 - bits-per-pixel : bit depth of framebuffer (16 or 32)
11 - display-timings: see display-timing.txt for information
16 compatible = "via,vt8500-fb";
19 bits-per-pixel = <16>;
21 display-timings {
22 native-mode = <&timing0>;
[all …]
H A Dmxsfb.txt6 - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
7 Should be "fsl,imx28-lcdif" for i.MX28.
8 Should be "fsl,imx6sx-lcdif" for i.MX6SX.
9 Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
10 - reg: Address and length of the register set for LCDIF
11 - interrupts: Should contain LCDIF interrupt
12 - clocks: A list of phandle + clock-specifier pairs, one for each
13 entry in 'clock-names'.
14 - clock-names: A list of clock names. For MXSFB it should contain:
15 - "pix" for the LCDIF block clock
[all …]
H A Dcirrus,clps711x-fb.txt4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timin
[all...]
H A Datmel,lcdc.txt2 -----------------------------------------------------
5 - compatible :
6 "atmel,at91sam9261-lcdc" ,
7 "atmel,at91sam9263-lcdc" ,
8 "atmel,at91sam9g10-lcdc" ,
9 "atmel,at91sam9g45-lcdc" ,
10 "atmel,at91sam9g45es-lcdc" ,
11 "atmel,at91sam9rl-lcdc" ,
12 - reg : Should contain 1 register ranges(address and length).
15 - interrupts : framebuffer controller interrupt
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the DVI-VGA Display";
[all...]
H A Dimx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the DVI-SVGA Display";
[all...]
H A Dimx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "imx25-eukrea-mbimxsd25-baseboard.dts"
9 model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
[all...]
/freebsd/sys/dev/drm2/
H A Ddrm_edid.h2 * Copyright © 2007-2008 Intel Corporation
141 struct std_timing timings[6]; member
191 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
214 /* Display info: */
231 /* Est. timings and mfg rsvd timings*/
233 /* Standard timings 1-8*/
235 /* Detailing timings 1-4 */
243 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))

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