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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-engine.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Pipeline
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
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H A Darm,malidp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/arm,malidp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Mali Display Processor (Mali-DP)
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
14 The following bindings apply to a family of Display Processors sold as
22 - arm,mali-dp500
23 - arm,mali-dp550
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H A Dallwinner,sun4i-a10-display-backend.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Backend
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine backend exposes layers and sprites to the system.
19 - allwinner,sun4i-a10-display-backend
20 - allwinner,sun5i-a13-display-backend
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/linux/drivers/soc/sunxi/
H A Dsunxi_mbus.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/dma-map-ops.h>
13 * The display engine virtual devices are not strictly speaking
18 "allwinner,sun4i-a10-display-engine",
19 "allwinner,sun5i-a10s-display-engine",
20 "allwinner,sun5i-a13-display-engine",
21 "allwinner,sun6i-a31-display-engine",
22 "allwinner,sun6i-a31s-display-engine",
23 "allwinner,sun7i-a20-display-engine",
24 "allwinner,sun8i-a23-display-engine",
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_drv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/dma-mapping.h>
40 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bp in drm_sun4i_gem_dumb_create()
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H A Dsun4i_backend.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
14 #include <linux/dma-mapping.h>
36 /* backend <-> TCON muxing selection done in backend */
49 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine) in sun4i_backend_apply_color_correction()
56 regmap_write(engine in sun4i_backend_apply_color_correction()
48 sun4i_backend_apply_color_correction(struct sunxi_engine * engine) sun4i_backend_apply_color_correction() argument
63 sun4i_backend_disable_color_correction(struct sunxi_engine * engine) sun4i_backend_disable_color_correction() argument
72 sun4i_backend_commit(struct sunxi_engine * engine,struct drm_crtc * crtc,struct drm_atomic_state * state) sun4i_backend_commit() argument
458 sun4i_backend_atomic_begin(struct sunxi_engine * engine,struct drm_crtc_state * old_state) sun4i_backend_atomic_begin() argument
469 sun4i_backend_atomic_check(struct sunxi_engine * engine,struct drm_crtc_state * crtc_state) sun4i_backend_atomic_check() argument
610 sun4i_backend_vblank_quirk(struct sunxi_engine * engine) sun4i_backend_vblank_quirk() argument
640 sun4i_backend_mode_set(struct sunxi_engine * engine,const struct drm_display_mode * mode) sun4i_backend_mode_set() argument
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H A Dsun4i_tcon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
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/linux/drivers/gpu/drm/amd/display/
H A DKconfig1 # SPDX-License-Identifier: MIT
2 # Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
4 menu "Display Engine Configuration"
8 bool "AMD DC - Enable new display engine"
17 Choose this option if you want to use the new display engine
26 https://github.com/llvm/llvm-project/issues/41896.
31 Floating point support, required for DCN-based SoCs
50 bool "Enable secure display support"
54 Choose this option if you want to support secure display
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c28 #include <engine/fifo.h>
35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
46 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
72 struct nv50_gr *gr = nv50_gr_chan(object)->gr; in nv50_gr_chan_bind()
73 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in nv50_gr_chan_bind()
77 nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); in nv50_gr_chan_bind()
96 return -ENOMEM; in nv50_gr_chan_new()
97 nvkm_object_ctor(&nv50_gr_chan, oclass, &chan->object); in nv50_gr_chan_new()
98 chan->gr = gr; in nv50_gr_chan_new()
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * - DC - display core (general settings)
15 * - DE - display engine
16 * - SE - scaling engine
113 /* Scaling engine registers and masks. */
194 #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8))
218 * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions
219 * - GREEN_ARQOS @ A 4-bit signal value for normal conditions
292 * 0x00000 Display Engine
293 * 0x08000 Scaling Engine
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/linux/Documentation/devicetree/bindings/bus/
H A Dallwinner,sun50i-a64-de2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A64 Display Engine Bus
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 pattern: "^bus(@[0-9a-f]+)?$"
17 "#address-cells":
20 "#size-cells":
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/linux/arch/powerpc/platforms/powernv/
H A Dopal-hmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 "Hypervisor Resource error - core check stop" }, in print_core_checkstop_reason()
74 if (!hmi_evt->u.xstop_error.xstop_reason) { in print_core_checkstop_reason()
80 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
82 if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) & in print_core_checkstop_reason()
84 printk("%s [Unit: %-3s] %s\n", level, in print_core_checkstop_reason()
94 { NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine", in print_nx_checkstop_reason()
96 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine", in print_nx_checkstop_reason()
98 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine", in print_nx_checkstop_reason()
100 { NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR, "DMA & Engine", in print_nx_checkstop_reason()
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-a13.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/thermal/thermal.h>
50 thermal-zones {
51 cpu-thermal {
53 polling-delay-passive = <250>;
54 polling-delay = <1000>;
55 thermal-sensors = <&rtp>;
57 cooling-maps {
60 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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H A Dsun5i-gr8.dtsi4 * Mylène Josserand <mylene.josserand@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
52 display-engine {
53 compatible = "allwinner,sun5i-a13-display-engine";
59 compatible = "allwinner,sun5i-a10s-pwm";
62 #pwm-cells = <3>;
67 #sound-dai-cells = <0>;
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H A Dsun5i-a10s.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/dma/sun4i-a10.h>
55 #address-cells = <1>;
56 #size-cells = <1>;
59 framebuffer-lcd0-hdmi {
60 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer";
62 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 display-engine {
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H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
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H A Dsun8i-a23.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
50 #sound-dai-cells = <0>;
51 compatible = "allwinner,sun8i-a23-codec";
55 clock-names = "apb", "codec";
58 dma-names = "rx", "tx";
59 allwinner,codec-analog-controls = <&codec_analog>;
66 compatible = "allwinner,sun8i-a23-display-backend";
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/linux/drivers/pmdomain/sunxi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 to enable power to certain peripherals, such as the display
12 engine.
25 tristate "Allwinner A523 PCK-600 power domain driver"
31 Say y to enable the PCK-600 power domain driver. This is required
32 to enable power to certain peripherals, such as the display and
/linux/Documentation/devicetree/bindings/display/hisilicon/
H A Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
3 ADE (Advanced Display Engine) is the display controller which grab image
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
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/linux/drivers/video/fbdev/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 a well-defined interface, so the software doesn't need to know
15 anything about the low-level (hardware register) stuff.
21 On several non-X86 architectures, the frame buffer device is the
29 and the Framebuffer-HOWTO at
30 <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.
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/linux/arch/sh/include/asm/
H A Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
81 /* DISPLAY-ENABLE polarity inversion */
84 /* DISPLAY DATA BUS polarity inversion */
96 /* Display types supported by the LCDC */
134 /* Set this member to a valid fb_videmode for the display you
144 /* LDMTR includes display type and signal polarity. The
148 * Display Enable signal (default high-active) DISPEN_LOWACT
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_drv.c60 * - 3.0.0 - initial driver
61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
64 * - 3.3.0 - Add VM support for UVD on supported hardware.
65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
66 * - 3.5.0 - Add support for new UVD_NO_OP register.
67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
68 * - 3.7.0 - Add support for VCE clock list packet
69 * - 3.8.0 - Add support raster config init in the kernel
70 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
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/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_dc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
95 #define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
116 #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) -
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/linux/Documentation/gpu/
H A Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
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/linux/arch/sh/boards/mach-se/7780/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <mach-se/mach/se7780.h>
25 .id = -1,
33 .name = "smc91x-regs" ,
74 /* "SH-Linux" on LED Display */ in se7780_setup()
77 __raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) ); in se7780_setup()
84 printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n"); in se7780_setup()
88 * REQ0/GNT0 -> USB in se7780_setup()
89 * REQ1/GNT1 -> PC Card in se7780_setup()
90 * REQ2/GNT2 -> Serial ATA in se7780_setup()
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