xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml (revision 3f1c07fc21c68bd3bd2df9d2c9441f6485e934d9) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Glymur Display MDSS
8
9maintainers:
10  - Abel Vesa <abel.vesa@linaro.org>
11
12description:
13  Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DP interfaces, etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,glymur-mdss
21
22  clocks:
23    items:
24      - description: Display AHB
25      - description: Display hf AXI
26      - description: Display core
27
28  iommus:
29    maxItems: 1
30
31  interconnects:
32    items:
33      - description: Interconnect path from mdp0 port to the data bus
34      - description: Interconnect path from CPU to the reg bus
35
36  interconnect-names:
37    items:
38      - const: mdp0-mem
39      - const: cpu-cfg
40
41patternProperties:
42  "^display-controller@[0-9a-f]+$":
43    type: object
44    additionalProperties: true
45    properties:
46      compatible:
47        const: qcom,glymur-dpu
48
49  "^displayport-controller@[0-9a-f]+$":
50    type: object
51    additionalProperties: true
52    properties:
53      compatible:
54        const: qcom,glymur-dp
55
56  "^phy@[0-9a-f]+$":
57    type: object
58    additionalProperties: true
59    properties:
60      compatible:
61        const: qcom,glymur-dp-phy
62
63required:
64  - compatible
65
66unevaluatedProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/clock/qcom,rpmh.h>
71    #include <dt-bindings/interconnect/qcom,icc.h>
72    #include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
73    #include <dt-bindings/interrupt-controller/arm-gic.h>
74    #include <dt-bindings/phy/phy-qcom-qmp.h>
75    #include <dt-bindings/power/qcom,rpmhpd.h>
76
77    display-subsystem@ae00000 {
78            compatible = "qcom,glymur-mdss";
79            reg = <0x0ae00000 0x1000>;
80            reg-names = "mdss";
81
82            interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
83
84            clocks = <&dispcc_ahb_clk>,
85                     <&gcc_disp_hf_axi_clk>,
86                     <&dispcc_mdp_clk>;
87            clock-names = "bus", "nrt_bus", "core";
88
89            interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
90                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
91                            <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
92                             &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
93            interconnect-names = "mdp0-mem",
94                                 "cpu-cfg";
95
96            resets = <&disp_cc_mdss_core_bcr>;
97
98            power-domains = <&mdss_gdsc>;
99
100            iommus = <&apps_smmu 0x1c00 0x2>;
101
102            interrupt-controller;
103            #interrupt-cells = <1>;
104
105            #address-cells = <1>;
106            #size-cells = <1>;
107            ranges;
108
109            display-controller@ae01000 {
110                compatible = "qcom,glymur-dpu";
111                reg = <0x0ae01000 0x8f000>,
112                      <0x0aeb0000 0x2008>;
113                reg-names = "mdp", "vbif";
114
115                clocks = <&gcc_axi_clk>,
116                         <&dispcc_ahb_clk>,
117                         <&dispcc_mdp_lut_clk>,
118                         <&dispcc_mdp_clk>,
119                         <&dispcc_mdp_vsync_clk>;
120                clock-names = "nrt_bus",
121                              "iface",
122                              "lut",
123                              "core",
124                              "vsync";
125
126                assigned-clocks = <&dispcc_mdp_vsync_clk>;
127                assigned-clock-rates = <19200000>;
128
129                operating-points-v2 = <&mdp_opp_table>;
130                power-domains = <&rpmhpd RPMHPD_MMCX>;
131
132                interrupt-parent = <&mdss>;
133                interrupts = <0>;
134
135                ports {
136                    #address-cells = <1>;
137                    #size-cells = <0>;
138
139                    port@0 {
140                        reg = <0>;
141                        dpu_intf1_out: endpoint {
142                            remote-endpoint = <&dsi0_in>;
143                        };
144                    };
145
146                    port@1 {
147                        reg = <1>;
148                        dpu_intf2_out: endpoint {
149                            remote-endpoint = <&dsi1_in>;
150                        };
151                    };
152                };
153
154                mdp_opp_table: opp-table {
155                    compatible = "operating-points-v2";
156
157                    opp-200000000 {
158                        opp-hz = /bits/ 64 <200000000>;
159                        required-opps = <&rpmhpd_opp_low_svs>;
160                    };
161
162                    opp-325000000 {
163                        opp-hz = /bits/ 64 <325000000>;
164                        required-opps = <&rpmhpd_opp_svs>;
165                    };
166
167                    opp-375000000 {
168                        opp-hz = /bits/ 64 <375000000>;
169                        required-opps = <&rpmhpd_opp_svs_l1>;
170                    };
171
172                    opp-514000000 {
173                        opp-hz = /bits/ 64 <514000000>;
174                        required-opps = <&rpmhpd_opp_nom>;
175                    };
176                };
177            };
178
179            displayport-controller@ae90000 {
180                compatible = "qcom,glymur-dp";
181                reg = <0xae90000 0x200>,
182                      <0xae90200 0x200>,
183                      <0xae90400 0x600>,
184                      <0xae91000 0x400>,
185                      <0xae91400 0x400>;
186
187                interrupt-parent = <&mdss>;
188                interrupts = <12>;
189
190                clocks = <&dispcc_mdss_ahb_clk>,
191                         <&dispcc_dptx0_aux_clk>,
192                         <&dispcc_dptx0_link_clk>,
193                         <&dispcc_dptx0_link_intf_clk>,
194                         <&dispcc_dptx0_pixel0_clk>,
195                         <&dispcc_dptx0_pixel1_clk>;
196                clock-names = "core_iface",
197                              "core_aux",
198                              "ctrl_link",
199                              "ctrl_link_iface",
200                              "stream_pixel",
201                              "stream_1_pixel";
202
203                assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
204                                  <&dispcc_mdss_dptx0_pixel0_clk_src>,
205                                  <&dispcc_mdss_dptx0_pixel1_clk_src>;
206                assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
207                                         <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
208                                         <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
209
210                operating-points-v2 = <&mdss_dp0_opp_table>;
211
212                power-domains = <&rpmhpd RPMHPD_MMCX>;
213
214                phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
215                phy-names = "dp";
216
217                #sound-dai-cells = <0>;
218
219                ports {
220                    #address-cells = <1>;
221                    #size-cells = <0>;
222
223                    port@0 {
224                        reg = <0>;
225
226                        mdss_dp0_in: endpoint {
227                          remote-endpoint = <&mdss_intf0_out>;
228                        };
229                    };
230
231                    port@1 {
232                        reg = <1>;
233
234                        mdss_dp0_out: endpoint {
235                        };
236                    };
237                };
238
239                mdss_dp0_opp_table: opp-table {
240                    compatible = "operating-points-v2";
241
242                    opp-160000000 {
243                        opp-hz = /bits/ 64 <160000000>;
244                        required-opps = <&rpmhpd_opp_low_svs>;
245                    };
246
247                    opp-270000000 {
248                        opp-hz = /bits/ 64 <270000000>;
249                        required-opps = <&rpmhpd_opp_svs>;
250                    };
251
252                    opp-540000000 {
253                        opp-hz = /bits/ 64 <540000000>;
254                        required-opps = <&rpmhpd_opp_svs_l1>;
255                    };
256
257                    opp-810000000 {
258                        opp-hz = /bits/ 64 <810000000>;
259                        required-opps = <&rpmhpd_opp_nom>;
260                    };
261                };
262            };
263        };
264...
265