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/linux/sound/hda/core/
H A Dcontroller.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio controller helpers
19 for (timeout = 1000; timeout > 0; timeout--) { in azx_clear_corbrp()
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", in azx_clear_corbrp()
29 for (timeout = 1000; timeout > 0; timeout--) { in azx_clear_corbrp()
222 unsigned int wp, rp; snd_hdac_bus_send_cmd_corb() local
261 unsigned int rp, wp; snd_hdac_bus_update_rirb() local
[all...]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042-evb-v2.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
16 stdout-path = "serial0";
19 pwmfan: pwm-fan {
20 compatible = "pwm-fan";
21 cooling-levels = <103 128 179 230 255>;
23 #cooling-cells = <2>;
26 thermal-zones {
[all …]
H A Dsg2042-evb-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
16 stdout-path = "serial0";
19 gpio-power {
20 compatible = "gpio-keys";
22 key-power {
26 linux,input-type = <EV_KEY>;
27 debounce-interval = <100>;
[all …]
H A Dcv1812h-huashan-pi.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
12 compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
31 #address-cells = <1>;
32 #size-cells = <1>;
37 no-map;
43 clock-frequency = <25000000>;
48 bus-width = <4>;
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
45 r = pm_runtime_get_sync(&pll->pdev->dev); in hdmi_pll_enable()
50 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
63 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
67 r = pm_runtime_put_sync(&pll->pdev->dev); in hdmi_pll_disable()
[all …]
H A Dhdmi4_cec.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
13 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
31 /* Not really a debug register, more a low-level control register */
58 u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; in hdmi_cec_received_msg()
69 if (msg.len > CEC_MAX_MSG_SIZE - 2) in hdmi_cec_received_msg()
70 msg.len = CEC_MAX_MSG_SIZE - 2; in hdmi_cec_received_msg()
71 msg.msg[0] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
73 msg.msg[1] = hdmi_read_reg(core->base, in hdmi_cec_received_msg()
79 hdmi_read_reg(core->base, reg); in hdmi_cec_received_msg()
[all …]
/linux/drivers/accel/ivpu/
H A Divpu_hw_btrs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2026 Intel Corporation
30 #define BTRS_IRQ_DISABLE_MASK ((u32)-1)
32 #define BTRS_LNL_ALL_IRQ_MASK ((u32)-1)
76 struct ivpu_hw_info *hw = vdev->hw; in freq_ratios_init_mtl()
80 hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse); in freq_ratios_init_mtl()
81 hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse); in freq_ratios_init_mtl()
84 hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse); in freq_ratios_init_mtl()
89 struct ivpu_hw_info *hw = vdev->hw; in freq_ratios_init_lnl()
93 hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse); in freq_ratios_init_lnl()
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-mighty.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "rk3288-veyron-jaq.dts"
14 compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4",
15 "google,veyron-mighty-rev3", "google,veyron-mighty-rev2",
16 "google,veyron-mighty-rev1", "google,veyron-mighty",
21 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
23 wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
25 /delete-property/ disable-wp;
30 sdmmc_wp_pin: sdmmc-wp-pin {
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
27 #include <sound/omap-hdmi-audio.h>
42 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
55 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
56 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
61 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
64 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
65 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
75 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
[all …]
H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <sound/omap-hdmi-audio.h>
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
65 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
68 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
69 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
93 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
[all …]
H A Dhdmi_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
47 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
49 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
56 n = DIV_ROUND_UP(clkin, hw->fint_max); in hdmi_pll_compute()
60 min_dco = roundup(hw->clkdco_min, fint); in hdmi_pll_compute()
71 if (WARN_ON(target_clkdco - clkdco > fint)) in hdmi_pll_compute()
74 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); in hdmi_pll_compute()
81 /* sigma-delta */ in hdmi_pll_compute()
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-pci-o2micro.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "sdhci-pci.h"
101 mmc_hostname(host->mmc)); in sdhci_o2_wait_card_detect_stable()
137 mmc_hostname(host->mmc)); in sdhci_o2_enable_internal_clock()
171 pci_read_config_dword(chip->pdev, in o2_pci_set_baseclk()
177 pci_write_config_dword(chip->pdev, in o2_pci_set_baseclk()
221 host->tuning_done = true; in __sdhci_o2_execute_tuning()
225 mmc_hostname(host->mmc)); in __sdhci_o2_execute_tuning()
233 mmc_hostname(host->mmc)); in __sdhci_o2_execute_tuning()
250 struct sdhci_pci_chip *chip = slot->chip; in sdhci_o2_dll_recovery()
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905x-p212.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on meson-gx-p23x-q20x.dtsi:
5 * - Copyright (c) 2016 Endless Computers, Inc.
7 * - Copyright (c) 2016 BayLibre, SAS.
13 #include "meson-gxl-s905x.dtsi"
22 stdout-path = "serial0:115200n8";
30 hdmi_5v: regulator-hdmi-5v {
31 compatible = "regulator-fixed";
33 regulator-name = "HDMI_5V";
34 regulator-min-microvolt = <5000000>;
[all …]
H A Dmeson-gxl-s905x-nexbox-a95x.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxl-s905x.dtsi"
13 compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl";
22 stdout-path = "serial0:115200n8";
30 vddio_card: gpio-regulator {
31 compatible = "regulator-gpio";
33 regulator-name = "VDDIO_CARD";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
[all …]
H A Dmeson-gxbb-p20x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "meson-gxbb.dtsi"
17 stdout-path = "serial0:115200n8";
25 usb_pwr: regulator-usb-pwrs {
26 compatible = "regulator-fixed";
28 regulator-name = "USB_PWR";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
35 enable-active-high;
38 vddio_card: gpio-regulator {
[all …]
H A Dmeson-gxl-s905w-jethome-jethub-j80.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "meson-gxl.dtsi"
15 compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";
22 reserved-memory {
37 stdout-path = "serial0:115200n8";
40 vddio_ao18: regulator-vddio-ao18 {
41 compatible = "regulator-fixed";
42 regulator-name = "VDDIO_AO18";
43 regulator-min-microvolt = <1800000>;
[all …]
H A Dmeson-gxbb-wetek.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
30 led-power {
31 /* red in suspend or power-off */
35 default-state = "on";
36 panic-indicator;
[all …]
H A Dmeson-gxl-s905x-hwacom-amazetv.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxl-s905x.dtsi"
13 compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl";
22 stdout-path = "serial0:115200n8";
30 vddio_card: gpio-regulator {
31 compatible = "regulator-gpio";
33 regulator-name = "VDDIO_CARD";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
[all …]
/linux/tools/perf/tests/
H A Dbp_account.c1 // SPDX-License-Identifier: GPL-2.0
4 * 'int-ll64.h' and avoid compile warnings when printing __u64 with %llu.
19 #include "parse-events.h"
20 #include "../perf-sys.h"
27 * Just disable the test for these architectures until these issues are
48 attr->type = PERF_TYPE_BREAKPOINT; in __event()
49 attr->size = sizeof(struct perf_event_attr); in __event()
51 attr->config = 0; in __event()
52 attr->bp_type = is_x ? HW_BREAKPOINT_X : HW_BREAKPOINT_W; in __event()
53 attr->bp_addr = (unsigned long) addr; in __event()
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
22 MODULE_PARM_DESC(disable_msi, "Set Y to disable MSI interrupt support");
23 MODULE_PARM_DESC(disable_aspm, "Set Y to disable PCI ASPM support");
48 return skb->priority; in rtw_pci_get_tx_qsel()
54 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
56 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
61 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read16()
63 return readw(rtwpci->mmap + addr); in rtw_pci_read16()
68 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read32()
[all …]
/linux/arch/arm/kernel/
H A Dhw_breakpoint.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
13 #define pr_fmt(fmt) "hw-breakpoint: " fmt
151 /* We don't support the memory-mapped interface. */ in debug_arch_supported()
216 return core_has_mismatch_brps() ? brps - 1 : brps; in get_num_brps()
257 return -ENODEV; in enable_monitor_mode()
265 return -EPERM; in enable_monitor_mode()
293 * Check if 8-bit byte-address select is available.
333 addr = info->address; in arch_install_hw_breakpoint()
334 ctrl = encode_ctrl_reg(info->ctrl) | 0x1; in arch_install_hw_breakpoint()
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8-fernsehfee3.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
27 stdout-path = "serial0:115200n8";
35 gpio-keys {
36 compatible = "gpio-keys-polled";
37 poll-interval = <100>;
39 power-button {
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-deepcomputing-fml13v01.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
15 cap-mmc-highspeed;
16 cap-mmc-hw-reset;
17 mmc-ddr-1_8v;
18 mmc-hs200-1_8v;
19 vmmc-supply = <&vcc_3v3>;
20 vqmmc-supply = <&emmc_vdd>;
24 rst-pins {
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
16 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
17 starfive,tx-use-rgmii-clk;
26 cap-mmc-highspeed;
27 cap-mmc-hw-reset;
28 mmc-ddr-1_8v;
[all …]

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