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Searched +full:disable +full:- +full:timing +full:- +full:generator (Results 1 – 25 of 52) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
45 /* Trigger Source Select - ASIC-defendant, actual values for the
74 /* Trigger Source Select - ASIC-dependant, actual values for the
126 /* determine if given timing can be supported by TG */
129 const struct dc_crtc_timing *timing,
134 /* Program timing generator with given timing */
139 /* Disable/Enable Timing Generator */
166 /*********** Timing Generator Synchronization routines ****/
188 /* disabling trigger-reset */
200 /* Fully program CRTC timing in timing generator */
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H A Ddce110_timing_generator.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
48 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
49 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
55 * So we can create dce110 timing generator to use it.
67 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
70 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
71 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
73 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
74 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
34 optc1->tg_regs->reg
37 optc1->base.ctx
41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
88 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
89 optc1->opp_coun in optc31_set_odm_combine()
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dadi,adv7533.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 - $ref: /schemas/sound/dai-common.yaml#
23 - adi,adv7533
24 - adi,adv7535
38 reg-names:
41 needing a non-default address.
44 - const: main
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/linux/drivers/video/fbdev/geode/
H A Ddisplay_gx1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * -- Geode GX1 display controller
58 return -ENOMEM; in gx1_frame_buffer_size()
74 return dram_size - fb_base; in gx1_frame_buffer_size()
79 struct geodefb_par *par = info->par; in gx1_set_mode()
85 readl(par->dc_regs + DC_UNLOCK); in gx1_set_mode()
86 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
88 gcfg = readl(par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
89 tcfg = readl(par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
91 /* Blank the display and disable the timing generator. */ in gx1_set_mode()
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/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
93 tg110->offsets.crtc); in dce120_timing_generator_is_in_vertical_blank()
100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
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/linux/drivers/tty/serial/
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
67 #define RxINT_DISAB 0 /* Rx Int Disable */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
137 #define nDTRnREQ 0x10 /* /DTR/REQ timing */
146 #define DLC 4 /* Disable Lower Chain */
170 #define TRxCBR 2 /* TRxC = BR Generator Output */
175 #define TCBR 0x10 /* Transmit clock = BR Generator output */
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/linux/drivers/mtd/nand/raw/
H A Dcafe_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/dma-mapping.h>
92 static int timing[3]; variable
93 module_param_array(timing, int, &numtimings, 0644);
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", in cafe_device_ready()
124 if (cafe->usedma) in cafe_write_buf()
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len); in cafe_write_buf()
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); in cafe_write_buf()
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
50 * timing tuning.
58 /* An internal counter based on the "timing-adjustment" clock. The counter is
71 /* Defined for adding a delay to the input RX_CLK for better timing.
110 data = readl(dwmac->reg in meson8b_dwmac_mask_bits()
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/linux/arch/sh/include/asm/
H A Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
81 /* DISPLAY-ENABLE polarity inversion */
90 /* Disable output of HSYNC during VSYNC period */
93 /* Disable output of VSYNC during VSYNC period */
148 * Display Enable signal (default high-active) DISPEN_LOWACT
149 * Display Data signals (default high-active) DPOL_LOWACT
151 * Hsync-During-Vsync suppression (default off) CL1CNT
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/linux/include/linux/spi/
H A Dsh_msiof.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
36 #define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */
37 #define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
46 #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
47 #define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
48 #define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */
51 #define SIMDR3_BITLEN2 GENMASK(28, 24) /* Data Size (8-32 bits) */
52 #define SIMDR3_WDLEN2 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
55 #define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.c1 // SPDX-License-Identifier: MIT
36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
47 * Enable CRTC - cal
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/linux/drivers/media/i2c/
H A Dths8200.c2 * ths8200 - Texas Instruments THS8200 video encoder driver
23 #include <linux/v4l2-dv-timings.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-device.h>
33 MODULE_PARM_DESC(debug, "debug level (0-2)");
93 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
94 * and then the value-mask (to be OR-ed).
108 reg->val = ths8200_read(sd, reg->reg & 0xff); in ths8200_g_register()
109 reg->size = 1; in ths8200_g_register()
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/
H A Ddcn32_optc.c36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
96 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
97 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
120 *odm_combine_segments = - in optc32_get_odm_combine_segments()
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/linux/drivers/media/usb/gspca/
H A Dstk1135.c1 // SPDX-License-Identifier: GPL-2.0-or-later
45 /* -- read a register -- */
48 struct usb_device *dev = gspca_dev->dev; in reg_r()
51 if (gspca_dev->usb_err < 0) in reg_r()
58 gspca_dev->usb_buf, 1, in reg_r()
62 index, gspca_dev->usb_buf[0]); in reg_r()
65 gspca_dev->usb_err = ret; in reg_r()
69 return gspca_dev->usb_buf[0]; in reg_r()
72 /* -- write a register -- */
76 struct usb_device *dev = gspca_dev->dev; in reg_w()
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/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
34 #define BBC_EBUST 0x20 /* [Q] EBUS Timing */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1 // SPDX-License-Identifier: MIT
46 hws->ctx
48 hws->regs->reg
50 dc->ctx->logger
55 hws->shifts->field_name, hws->masks->field_name
59 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
61 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn401_initialize_min_clocks()
62 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
63 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
64 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c93 dc->ctx
96 dc->ctx->logger
98 static const char DC_BUILD_ID[] = "production-build";
103 * DC is the OS-agnostic component of the amdgpu DC driver.
110 * struct dc - The central struct. One per driver. Created on driver load,
113 * struct dc_context - One per driver.
116 * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
119 * struct dc_sink - One per display. Created on boot or hotplug.
122 * sinks (in the Multi-Stream Transport case)
124 * struct resource_pool - One per driver. Represents the hw blocks not in the
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
73 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
126 // for example, 1080p -> 8K is 4.0, or 4000 raw value
134 // for example, 8K -> 1080p is 0.25, or 250 raw value
146 * DOC: color-management-caps
151 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
158 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
174 * struct dpp_color_caps - color pipeline capabilities for display pipe and
179 * just plain 256-entry lookup
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/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
13 2) Timing Devices
21 the virtualization of this platform is the plethora of timing devices available
32 information relevant to KVM and hardware-based virtualization.
34 2. Timing Devices
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
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/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
31 optc1->tg_regs->reg
34 optc1->base.ctx
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
41 * optc2_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
60 OPTC_SEG0_SRC_SEL, optc->inst); in optc2_enable_crtc()
80 * optc2_set_gsl() - Assign OTG to GSL groups,
97 OTG_GSL0_EN, params->gsl0_en, in optc2_set_gsl()
98 OTG_GSL1_EN, params->gsl1_en, in optc2_set_gsl()
99 OTG_GSL2_EN, params->gsl2_en, in optc2_set_gsl()
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/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[(dev)] = \
79 next->ptfv_list[(dev)] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[(dev)] += \
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/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt73usb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
27 * Default offset is required for RSSI <-> dBm conversion.
76 * 16 entries 32-byte for shared key table
77 * 64 entries 32-byte for pairwise key table
78 * 64 entries 8-byte for pairwise ta key table
113 * On-chip BEACON frame space.
183 * 0: 1-BSSID mode (BSS index = 0)
184 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
185 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
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H A Drt2500usb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
36 * Default offset is required for RSSI <-> dBm conversion.
238 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
249 * DISABLE_RX: Disable rx engine.
315 * TXRX_CSR9: TX ACK time-out.
350 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
352 * BEACON_GEN: Enable beacon generator.
463 * PHY_CSR0: RF switching timing control.
498 * BBP pre-TX registers.
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/linux/drivers/comedi/drivers/
H A Daddi_apci_3120.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
6 * ADDI-DATA GmbH
8 * D-77833 Ottersweier
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
12 * info@addi-data.com
22 * PCI BAR 0 register map (devpriv->amcc)
28 * PCI BAR 1 register map (dev->iobase)
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