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/freebsd/sys/contrib/device-tree/Bindings/sram/
H A Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Darm,pl353-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
16 SRAM or NOR).
23 const: arm,pl353-smc-r2p1
25 - compatible
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H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
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H A Darm,pl35x-smc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 SRAM or NOR) depending on the specific configuration.
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
27 - arm,pl354
29 - compatible
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dallwinner,sun4i-a10-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
18 const: allwinner,sun4i-a10-emac
29 allwinner,sram:
30 description: Phandle to the device SRAM
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H A Dmarvell-neta-bm.txt5 - compatible: should be "marvell,armada-380-neta-bm".
6 - reg: address and length of the register set for the device.
7 - clocks: a pointer to the reference clock for this device.
8 - internal-mem: a phandle to BM internal SRAM definition.
12 - pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
17 - pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
23 refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.
27 - main node:
30 compatible = "marvell,armada-380-neta-bm";
33 internal-mem = <&bm_bppi>;
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
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/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpm
[all...]
H A Dnvidia,tegra186-bpmp.txt11 - compatible
14 - "nvidia,tegra186-bpmp"
15 - mboxes : The phandle of mailbox controller and the mailbox specifier.
16 - shmem : List of the phandle of the TX and RX shared memory area that
18 - #clock-cells : Should be 1.
19 - #power-domain-cells : Should be 1.
20 - #reset-cells : Should be 1.
26 - .../mailbox/mailbox.txt
27 - .../mailbox/nvidia,tegra186-hsp.txt
33 - .../clock/clock-bindings.txt
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dcache_sram.txt1 * Freescale PQ3 and QorIQ based Cache SRAM
5 as SRAM. This cache SRAM representation in the device
6 tree should be done as under:-
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ti/
H A Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
26 - ti,hwmods : For TI hwmods processing and omap device creation
29 - interrupts : interrupt used by the controller
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
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H A Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
25 host processor (Arm CorePac) to perform the device management of the remote
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H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5
[all...]
H A Dmtk,scp.txt2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be "mediatek,mt8183-scp"
9 - reg Should contain the address ranges for memory regions:
10 SRAM, CFG, and L1TCM.
11 - reg-names Contains the corresponding names for the memory regions:
12 "sram", "cfg", and "l1tcm".
13 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
14 - clock-names Contains the corresponding name for the clock. This
18 --------
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/freebsd/share/man/man4/
H A Dhifn.437 .Bd -ragged -offset indent
38 .Cd "device crypto"
39 .Cd "device cryptodev"
40 .Cd "device hifn"
46 .Bd -literal -offset indent
59 SHA1, and SHA1-HMAC operations for
79 .Bl -tag -width namenamenamena -offset indent
82 Came as 128KB SRAM model, or 2MB DRAM model.
84 Reference board with 512KB SRAM.
86 Comes with 512KB SRAM.
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,scmi.txt2 ----------------------------------------------------------
11 the device tree.
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
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H A Darm,scpi.txt2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dallwinner,sun4i-a10-video-engine.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun4i-a10-video-engine
17 - allwinner,sun5i-a13-video-engine
18 - allwinner,sun7i-a20-video-engine
19 - allwinner,sun8i-a33-video-engine
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmotionpro.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Motion-PRO board Device Tree Source
11 &gpt0 { fsl,has-wdt; };
12 &gpt6 { // Motion-PRO status LED
13 compatible = "promess,motionpro-led";
14 label = "motionpro-statusled";
15 blink-delay = <100>; // 100 msec
17 &gpt7 { // Motion-PRO ready LED
18 compatible = "promess,motionpro-led";
19 label = "motionpro-readyled";
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dgpu.txt4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
5 "amd,imageon-XYZ.W", "amd,imageon"
6 for example: "qcom,adreno-306.0", "qcom,adreno"
8 is what the device is matched on), in addition to the more specific
9 with the chip-id.
10 If "amd,imageon" is used, there should be no top level msm device.
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt signal from the gpu.
13 - clocks: device clocks (if applicable)
14 See ../clocks/clock-bindings.txt for details.
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dallwinner,sun50i-a64-de2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 pattern: "^bus(@[0-9a-f]+)?$"
17 "#address-cells":
20 "#size-cells":
25 - const: allwinner,sun50i-a64-de2
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/freebsd/sys/dev/qat/qat_api/qat_direct/include/
H A Dicp_adf_cfg.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
11 * This is the top level header file for the run-time system configuration
13 * access the supported run-time configuration parameters.
46 /* SRAM Physical Address Key */
48 /* SRAM Virtual Address Key */
50 /* SRAM Size In Bytes Key */
52 /* Device node id, tells to which die the device is
55 /* Device package id, this is accel_dev id */
57 /* Device bus address, B.D.F (Bus(8bits),Device(5bits),Function(3bits)) */
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/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91sam9xe.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
6 * 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
15 sram0: sram@2ff000 {
19 sram1: sram@300000 {
20 compatible = "mmio-sram";
22 #address-cells = <1>;
23 #size-cells = <1>;
/freebsd/sys/contrib/device-tree/Bindings/fsi/
H A Dfsi-master-ast-cf.txt1 Device-tree bindings for ColdFire offloaded gpio-based FSI master driver
2 ------------------------------------------------------------------------
5 - compatible =
6 "aspeed,ast2400-cf-fsi-master" for an AST2400 based system
8 "aspeed,ast2500-cf-fsi-master" for an AST2500 based system
10 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
11 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
12 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
13 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
14 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
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