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/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 6 …fferent Node or Group (Distant), as this chip due to either only demand loads or demand loads plus… 11 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 12 …fferent Node or Group (Distant), as this chip due to either only demand loads or demand loads plus… 17 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", 18 …p's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus… 23 …fDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load", 24 … data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 35 …sor's data cache was reloaded from a location other than the local core's L2 due to a demand load", [all …]
H A D	memory.json	5 …ip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch… 6 …cross this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst pre… 11 …fDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load", 12 …Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load" 17 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load", 18 …'s memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus… 23 …tion": "The processor's data cache was reloaded from the local chip's Memory due to a demand load", 24 …che was reloaded from the local chip's Memory due to either only demand loads or demand loads plus… 29 …as reloaded from a memory location including L4 from local remote or distant due to a demand load", 30 …ion including L4 from local remote or distant due to either only demand loads or demand loads plus… [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	datasource.json	15 …cessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss." 20 … "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss." 30 …he processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." 55 …"BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread t… 60 …n": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss." 65 …ption": "The processor's L1 data cache was reloaded from the local core's L2 due to a demand miss." 70 …essor's instruction cache was reloaded from the local core's L2 due to a demand miss or prefetch r… 75 …processor's L1 data cache was reloaded from the local core's L2 due to a demand miss or prefetch r… 80 …or's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss." 85 …cessor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss." [all …]
H A D	memory.json	5 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16\|17] is 1, this count includes … 10 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes… 15 …G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes… 20 …d. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes… 30 …T. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes… 40 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16\|17] is 1, this count includes … 45 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes… 50 …K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes… 55 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes… 60 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes… [all …]
H A D	marked.json	15 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16\|17] is 1, this count includes … 20 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif… 25 …d. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes… 50 "BriefDescription": "Marked demand reload." 95 …only lines that were reloaded to satisfy a demand miss. If MMCR1[16\|17] is 1, this count includes … 100 …"BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specif… 120 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes… 125 …s data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked … 130 "BriefDescription": "Marked demand data load miss counted at finish time." 135 …eloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked … [all …]
H A D	frontend.json	5 …16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes… 10 …K. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes… 15 …ccess). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes … 25 … miss. All page sizes are counted by this event. This event only counts instruction demand access." 55 …e. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes… 60 …K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes… 70 …e processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss." 95 …n. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes… 105 …Description": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses."
H A D	metrics.json	424 …"BriefDescription": "Percentage of completed instructions that were a demand load that did not hit… 431 …"BriefDescription": "Percentage of completed instructions that were demand fetches that missed the… 438 …"BriefDescription": "Percentage of completed instructions that were demand fetches that missed the… 445 …"BriefDescription": "Percentage of completed instructions that were demand fetches that reloaded f… 477 …"BriefDescription": "Percentage of demand loads that reloaded from the L2 per completed instructio… 484 …"BriefDescription": "Percentage of demand loads that reloaded from beyond the L2 per completed ins… 491 …"BriefDescription": "Percentage of demand loads that reloaded using modified data from another cor… 498 …"BriefDescription": "Percentage of demand loads that reloaded using shared data from another core'… 505 …"BriefDescription": "Percentage of demand loads that reloaded from the L3 per completed instructio… 512 …"BriefDescription": "Percentage of demand loads that reloaded with data brought into the L3 by pre… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	cache.json	25 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 101 "BriefDescription": "Demand Data Read requests", 105 …"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D … 110 "BriefDescription": "Demand requests that miss L2 cache", 114 "PublicDescription": "Demand requests that miss L2 cache.", 119 "BriefDescription": "Demand requests to L2 cache", 123 "PublicDescription": "Demand requests to L2 cache.", 141 …ad for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well… 164 "BriefDescription": "Demand Data Read requests that hit L2 cache", 168 …"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructio… [all …]
H A D	memory.json	3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 12 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 204 "BriefDescription": "Demand Data Read requests who miss L3 cache", 208 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 213 …"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the sup… 222 …"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 c… 230 …"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the su… 239 "BriefDescription": "Counts all demand code reads", 249 "BriefDescription": "Counts all demand code reads", 259 "BriefDescription": "Counts all demand code reads", [all …]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	cache.json	12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 16 …er of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 27 …er of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 36 …mber of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests… 45 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 87 …fDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 91 … that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicte… 105 "BriefDescription": "Demand Data Read requests", [all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	cache.json	12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 16 …er of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 27 …er of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 36 …mber of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests… 45 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 87 …fDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 91 … that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicte… 105 "BriefDescription": "Demand Data Read requests", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	cache.json	12 … "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability", 17 … "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", 122 "BriefDescription": "Clean L2 cache lines evicted by demand", 126 "PublicDescription": "Clean L2 cache lines evicted by demand.", 131 "BriefDescription": "Dirty L2 cache lines evicted by demand", 135 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 176 "BriefDescription": "Demand Data Read requests", 180 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 221 "BriefDescription": "Demand Data Read requests that hit L2 cache", 225 "PublicDescription": "Demand Data Read requests that hit L2 cache.", [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	cache.json	20 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 24 …er of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 29 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 35 …er of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 40 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 44 …mber of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests… 53 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 95 …fDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 99 … that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicte… 140 "BriefDescription": "Demand Data Read access L2 cache", [all …]
H A D	virtual-memory.json	12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 17 …unts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 26 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T… 31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", 35 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im… 40 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", 44 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This… 49 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", 53 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im… 58 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", [all …]
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	cache.json	12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 16 …er of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 27 …er of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 36 …mber of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests… 45 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 96 "BriefDescription": "Demand Data Read access L2 cache", 100 …"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may … 109 …ad for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well… [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	cache.json	12 … "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", 25 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 95 "BriefDescription": "Clean L2 cache lines evicted by demand.", 112 "BriefDescription": "Demand Data Read requests", 116 …"PublicDescription": "This event counts the number of demand Data Read requests (including request… 121 "BriefDescription": "Demand requests that miss L2 cache.", 129 "BriefDescription": "Demand requests to L2 cache.", 150 …ad for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well… 171 "BriefDescription": "Demand Data Read requests that hit L2 cache", 175 …"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructio… [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	virtual-memory.json	12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 17 …unts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 26 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T… 31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", 35 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im… 40 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", 44 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This… 49 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", 53 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im… 58 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", [all …]
H A D	cache.json	20 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 24 …er of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 29 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 35 …er of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 49 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 53 …mber of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests… 62 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 104 …fDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 108 … that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicte… 140 "BriefDescription": "Demand Data Read access L2 cache", [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	virtual-memory.json	12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 17 …unts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 26 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T… 31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", 35 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im… 40 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", 44 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This… 49 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", 53 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im… 58 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", [all …]
H A D	cache.json	20 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 24 …er of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 29 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 35 …er of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 49 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 53 …mber of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests… 62 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 104 …fDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 108 … that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicte… 140 "BriefDescription": "Demand Data Read access L2 cache", [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	virtual-memory.json	12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 17 …unts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 26 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T… 31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", 35 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im… 40 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", 44 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This… 49 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", 53 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im… 58 … "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", [all …]
H A D	cache.json	12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav… 16 …er of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav… 27 …er of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand reques… 32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res… 36 …mber of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests… 45 …Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at… 96 "BriefDescription": "Demand Data Read requests", 100 …"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D … 105 "BriefDescription": "Demand requests that miss L2 cache", [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	cache.json	12 … "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", 102 "BriefDescription": "Clean L2 cache lines evicted by demand", 106 "PublicDescription": "Clean L2 cache lines evicted by demand.", 111 "BriefDescription": "Dirty L2 cache lines evicted by demand", 115 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 129 "BriefDescription": "Demand Data Read requests", 134 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 139 "BriefDescription": "Demand requests that miss L2 cache", 144 "PublicDescription": "Demand requests that miss L2 cache.", 149 "BriefDescription": "Demand requests to L2 cache", [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	virtual-memory.json	3 "BriefDescription": "Page walk completed due to a demand load to a 1GB page", 7 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 12 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page", 16 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 21 "BriefDescription": "Page walk completed due to a demand load to a 4K page", 25 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 30 "BriefDescription": "Page walks outstanding due to a demand load every cycle.", 34 …ion": "Counts once per cycle for each page walk occurring due to a load (demand data loads or SW p… 39 "BriefDescription": "Page walk completed due to a demand data store to a 1GB page", 43 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	cache.json	12 … "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", 102 "BriefDescription": "Clean L2 cache lines evicted by demand", 106 "PublicDescription": "Clean L2 cache lines evicted by demand.", 111 "BriefDescription": "Dirty L2 cache lines evicted by demand", 115 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 129 "BriefDescription": "Demand Data Read requests", 134 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 139 "BriefDescription": "Demand requests that miss L2 cache", 144 "PublicDescription": "Demand requests that miss L2 cache.", 149 "BriefDescription": "Demand requests to L2 cache", [all …]

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