Searched full:ddrpll (Results 1 – 10 of 10) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | calxeda.yaml | 59 ddrpll: ddrpll@108 {
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| H A D | zynq-7000.txt | 42 1: ddrpll
96 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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| H A D | nuvoton,ma35d1-clk.yaml | 36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
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| H A D | keystone-pll.txt | 4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
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| /freebsd/sys/contrib/device-tree/src/arm/calxeda/ |
| H A D | ecx-common.dtsi | 145 ddrpll: ddrpll { label
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| /freebsd/sys/contrib/device-tree/src/arm64/nuvoton/ |
| H A D | ma35d1-som-256m.dts | 42 <&clk DDRPLL>,
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| H A D | ma35d1-iot-512m.dts | 42 <&clk DDRPLL>,
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.h | 21 #define DDRPLL 10 macro
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| /freebsd/sys/contrib/device-tree/src/arm/xilinx/ |
| H A D | zynq-7000.dtsi | 320 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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| /freebsd/sys/dev/qcom_gcc/ |
| H A D | qcom_gcc_ipq4018_clock.c | 204 * DDRPLL - 48MHz (xo) input, 5.376GHz output
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