| /linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/ |
| H A D | uncore-ddrc.json | 5 "BriefDescription": "DDRC total write operations",
6 "PublicDescription": "DDRC total write operations",
7 "Unit": "hisi_sccl,ddrc"
12 "BriefDescription": "DDRC total read operations",
13 "PublicDescription": "DDRC total read operations",
14 "Unit": "hisi_sccl,ddrc"
19 "BriefDescription": "DDRC write commands",
20 "PublicDescription": "DDRC write commands",
21 "Unit": "hisi_sccl,ddrc"
26 "BriefDescription": "DDRC read commands",
[all …]
|
| H A D | uncore-hha.json | 48 "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
49 "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 64bytes",
55 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
56 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
62 … "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
63 … "PublicDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
69 … "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
70 … "PublicDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
|
| /linux/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| H A D | imx8m-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
13 The DDRC block is integrated in i.MX8M for interfacing with DDR based
20 The Linux driver for the DDRC doesn't even map registers (they're included
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
31 - const: fsl,imx8m-ddrc
36 Base address and size of DDRC CTL area.
37 This is not currently mapped by the imx8m-ddrc driver.
64 ddrc: memory-controller@3d400000 {
[all …]
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | snps,dw-umctl2-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
28 const: snps,ddrc-3.80a
30 const: snps,dw-umctl2-ddrc
32 const: xlnx,zynqmp-ddrc-2.40a
36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
61 reference clock, DDRC core clock, Scrubber standalone clock
62 (synchronous to the DDRC clock).
96 compatible = "xlnx,zynqmp-ddrc-2.40a";
107 compatible = "snps,dw-umctl2-ddrc";
|
| H A D | xlnx,zynq-ddrc-a05.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
|
| /linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | fsl,imx8m-noc.yaml | 53 fsl,ddrc:
81 fsl,ddrc = <&ddrc>;
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
|
| /linux/tools/perf/pmu-events/arch/test/test_soc/cpu/ |
| H A D | uncore.json | 5 "BriefDescription": "DDRC write commands",
6 "PublicDescription": "DDRC write commands",
7 "Unit": "hisi_sccl,ddrc"
|
| /linux/arch/arm/mach-zynq/ |
| H A D | pm.c | 58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()
60 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()
63 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
|
| /linux/drivers/devfreq/ |
| H A D | imx8m-ddrc.c | 262 dev_err(dev, "ddrc failed freq switch to %lu from %lu: error %d. now at %lu\n", in imx8m_ddrc_target()
265 dev_err(dev, "ddrc failed freq update to %lu from %lu, now at %lu\n", in imx8m_ddrc_target()
268 dev_dbg(dev, "ddrc freq set to %lu (was %lu)\n", in imx8m_ddrc_target()
441 { .compatible = "fsl,imx8m-ddrc", },
449 .name = "imx8m-ddrc-devfreq",
|
| H A D | Makefile | 13 obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
|
| H A D | Kconfig | 102 tristate "i.MX8M DDRC DEVFREQ Driver"
|
| /linux/Documentation/admin-guide/perf/ |
| H A D | alibaba_pmu.rst | 28 based on DDRC core clock.
53 By counting the READ, WRITE and RMW commands sent to the DDRC through the HIF
|
| /linux/drivers/edac/ |
| H A D | synopsys_edac.c | 200 /* DDRC Software control register */
203 /* DDRC ECC CE & UE poison mask */
207 /* DDRC Device config masks */
974 .compatible = "xlnx,zynq-ddrc-a05",
978 .compatible = "xlnx,zynqmp-ddrc-2.40a",
982 .compatible = "snps,ddrc-3.80a",
|
| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mm-evk.dts | 20 &ddrc {
|
| H A D | imx8mn-ddr4-evk.dts | 32 &ddrc {
|
| H A D | imx8mm-kontron-sl.dtsi | 43 &ddrc {
|
| H A D | imx8mn.dtsi | 1302 ddrc: memory-controller@3d400000 { label
1303 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
|
| H A D | imx8mm-phycore-som.dtsi | 50 &ddrc {
|
| H A D | imx8mm-innocomm-wb15.dtsi | 38 &ddrc {
|
| H A D | imx8mn-beacon-som.dtsi | 54 &ddrc {
|
| /linux/arch/arm64/boot/dts/intel/ |
| H A D | socfpga_n5x_socdk.dts | 30 compatible = "snps,ddrc-3.80a";
|
| /linux/arch/mips/include/asm/mach-rc32434/ |
| H A D | ddr.h | 40 u32 ddrc; member
|
| /linux/tools/perf/tests/ |
| H A D | pmu-events.c | 132 .desc = "DDRC write commands",
134 .long_desc = "DDRC write commands",
135 .pmu = "hisi_sccl,ddrc",
138 .alias_long_desc = "DDRC write commands",
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra20-pinmux.yaml | 47 ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
|
| /linux/drivers/clk/hisilicon/ |
| H A D | clk-hi3660-stub.c | 108 DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc")
|