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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon_dclk.c28 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_disable() local
30 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_disable()
36 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_enable() local
38 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_enable()
45 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_is_enabled() local
48 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); in sun4i_dclk_is_enabled()
56 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_recalc_rate() local
59 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); in sun4i_dclk_recalc_rate()
73 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_round_rate() local
74 struct sun4i_tcon *tcon = dclk->tcon; in sun4i_dclk_round_rate()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c49 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_recalc_rate() local
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
55 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in hi6220_clkdiv_recalc_rate()
61 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_round_rate() local
63 return divider_round_rate(hw, rate, prate, dclk->table, in hi6220_clkdiv_round_rate()
64 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in hi6220_clkdiv_round_rate()
73 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_set_rate() local
75 value = divider_get_val(rate, parent_rate, dclk->table, in hi6220_clkdiv_set_rate()
[all …]
/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-divider.c33 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_recalc_rate() local
35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in ma35d1_clkdiv_recalc_rate()
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in ma35d1_clkdiv_recalc_rate()
44 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_round_rate() local
46 return divider_round_rate(hw, rate, prate, dclk->table, in ma35d1_clkdiv_round_rate()
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_round_rate()
55 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_set_rate() local
57 value = divider_get_val(rate, parent_rate, dclk->table, in ma35d1_clkdiv_set_rate()
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/linux/Documentation/devicetree/bindings/display/
H A Dsolomon,ssd1307fb.yaml87 solomon,dclk-div:
94 solomon,dclk-frq:
138 solomon,dclk-div:
140 solomon,dclk-frq:
156 solomon,dclk-div:
158 solomon,dclk-frq:
174 solomon,dclk-div:
176 solomon,dclk-frq:
192 solomon,dclk-div:
194 solomon,dclk-frq:
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/linux/drivers/siox/
H A Dsiox-bus-gpio.c20 struct gpio_desc *dclk; member
38 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
60 gpiod_set_value_cansleep(ddata->dclk, 1); in siox_gpio_pushpull()
62 gpiod_set_value_cansleep(ddata->dclk, 0); in siox_gpio_pushpull()
112 ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW); in siox_gpio_probe()
113 if (IS_ERR(ddata->dclk)) in siox_gpio_probe()
114 return dev_err_probe(dev, PTR_ERR(ddata->dclk), in siox_gpio_probe()
115 "Failed to get dclk GPIO\n"); in siox_gpio_probe()
/linux/drivers/clk/
H A Dclk-lmk04832.c246 * @dclk: list of internal device clock references.
267 struct lmk_dclk *dclk; member
715 * and dclk
1013 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_is_enabled() local
1014 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled()
1018 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_is_enabled()
1028 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_prepare() local
1029 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare()
1032 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_prepare()
1038 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); in lmk04832_dclk_unprepare() local
[all …]
/linux/sound/soc/meson/
H A Daxg-pdm.c94 struct clk *dclk; member
186 /* Max sample counter value per half period of dclk */ in axg_pdm_set_sample_pointer()
188 clk_get_rate(priv->dclk) * 2); in axg_pdm_set_sample_pointer()
253 ret = clk_set_rate(priv->dclk, rate * os); in axg_pdm_hw_params()
255 dev_err(dai->dev, "failed to set dclk\n"); in axg_pdm_hw_params()
276 ret = clk_prepare_enable(priv->dclk); in axg_pdm_startup()
278 dev_err(dai->dev, "enabling dclk failed\n"); in axg_pdm_startup()
294 clk_disable_unprepare(priv->dclk); in axg_pdm_shutdown()
618 priv->dclk = devm_clk_get(dev, "dclk"); in axg_pdm_probe()
619 if (IS_ERR(priv->dclk)) in axg_pdm_probe()
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/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
H A Dradeon_uvd.c933 * @dclk: wanted DCLK
943 * @optimal_dclk_div: resulting dclk post divider
949 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
964 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
984 /* calc dclk divider with current vco freq */ in radeon_uvd_calc_upll_dividers()
985 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
H A Dsumo_dpm.c822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
839 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock()
857 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock()
1413 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info()
1416 rps->dclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
863 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index()
1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info()
1648 rps->dclk = 0; in trinity_parse_pplib_non_clock_info()
1890 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table()
1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1998 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
H A Drv6xx_dpm.c1519 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
/linux/drivers/video/fbdev/riva/
H A Dnv_driver.c276 unsigned long dclk = 0; in riva_get_maxdclk() local
286 dclk = 800000; in riva_get_maxdclk()
288 dclk = 1000000; in riva_get_maxdclk()
294 dclk = 1000000; in riva_get_maxdclk()
303 dclk = 800000; in riva_get_maxdclk()
306 dclk = 1000000; in riva_get_maxdclk()
311 return dclk; in riva_get_maxdclk()
/linux/Documentation/devicetree/bindings/siox/
H A Deckelmann,siox-gpio.txt5 - din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the
17 dclk-gpios = <&gpio6 9 0>;
/linux/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_crtc.c72 clk_prepare_enable(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_set_display_timing()
73 clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); in rzg2l_du_crtc_set_display_timing()
210 clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_put()
407 rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk"); in rzg2l_du_crtc_create()
408 if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) { in rzg2l_du_crtc_create()
410 return PTR_ERR(rcrtc->rzg2l_clocks.dclk); in rzg2l_du_crtc_create()
/linux/drivers/video/fbdev/core/
H A Dfbmon.c546 DPRINTK(" mode exceed max DCLK\n"); in get_std_timing()
770 DPRINTK(" H: %d-%dKHz V: %d-%dHz DCLK: %dMHz\n", in fb_get_monitor_limits()
1017 u32 dclk; member
1087 * @dclk: pixelclock in Hz
1099 * where: h_period = SQRT(100 - C + (0.4 * xres * M)/dclk) + C - 100
1105 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) in fb_get_hblank_by_dclk() argument
1109 dclk /= 1000; in fb_get_hblank_by_dclk()
1112 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk); in fb_get_hblank_by_dclk()
1156 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_vfreq()
1167 timings->dclk = timings->htotal * timings->hfreq; in fb_timings_hfreq()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Damlogic,axg-pdm.yaml37 - const: dclk
81 clock-names = "pclk", "dclk", "sysclk";
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.c176 /* vop dclk */
177 struct clk *dclk; member
181 /* vop dclk reset */
634 ret = clk_enable(vop->dclk); in vop_enable()
702 clk_disable(vop->dclk); in vop_enable()
775 clk_disable(vop->dclk); in vop_crtc_atomic_disable()
1243 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_mode_fixup()
1245 rate = clk_round_rate(vop->dclk, in vop_crtc_mode_fixup()
1477 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); in vop_crtc_atomic_enable()
2017 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); in vop_initial()
[all …]
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml71 - const: dclk
118 reset-names = "axi", "ahb", "dclk";
H A Drockchip-vop2.yaml71 Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI,
77 Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_5_ppsmc.h52 #define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
59 #define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
H A Dsmu_v13_0_1_ppsmc.h65 …efine PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
75 …efine PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h145 uint32_t DCLK; member
185 unsigned long dclk; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h39 uint32_t dclk; member
120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
/linux/drivers/clk/mvebu/
H A Darmada-39x.c21 * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
88 { .id = A390_CPU_TO_DCLK, .name = "dclk" },

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