Lines Matching full:dclk
33 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_recalc_rate() local
35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in ma35d1_clkdiv_recalc_rate()
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in ma35d1_clkdiv_recalc_rate()
44 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_round_rate() local
46 return divider_round_rate(hw, rate, prate, dclk->table, in ma35d1_clkdiv_round_rate()
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_round_rate()
55 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); in ma35d1_clkdiv_set_rate() local
57 value = divider_get_val(rate, parent_rate, dclk->table, in ma35d1_clkdiv_set_rate()
58 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_set_rate()
60 spin_lock_irqsave(dclk->lock, flags); in ma35d1_clkdiv_set_rate()
62 data = readl_relaxed(dclk->reg); in ma35d1_clkdiv_set_rate()
63 data &= ~(clk_div_mask(dclk->width) << dclk->shift); in ma35d1_clkdiv_set_rate()
64 data |= (value - 1) << dclk->shift; in ma35d1_clkdiv_set_rate()
65 data |= dclk->mask; in ma35d1_clkdiv_set_rate()
66 writel_relaxed(data, dclk->reg); in ma35d1_clkdiv_set_rate()
68 spin_unlock_irqrestore(dclk->lock, flags); in ma35d1_clkdiv_set_rate()