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/linux/sound/soc/fsl/
H A Dfsl_esai.c1 // SPDX-License-Identifier: GPL-2.0
17 #include "imx-pcm.h"
25 * struct fsl_esai_soc_data - soc specific data
33 * struct fsl_esai - ESAI private data
38 * @coreclk: clock source to access register
39 * @extalclk: esai clock source to derive HCK, SCK and FS
40 * @fsysclk: system clock source to derive HCK, SCK and FS
41 * @spbaclk: SPBA clock (optional, depending on SoC design)
43 * @soc: soc specific data
51 * @hck_rate: clock rate of desired HCKx clock
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H A Dfsl_asrc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
14 #include <linux/dma/imx-dma.h>
26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
125 * Check if the divider is available for internal ratio mode
159 * fsl_asrc_sel_proc - Select the pre-processing and post-processing options
162 * @pre_proc: return value for pre-processing option
163 * @post_proc: return value for post-processing option
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H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
58 return !sai->synchronous[dir] && sai->synchronou in fsl_sai_dir_is_synced()
178 fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio) fsl_sai_set_dai_bclk_ratio() argument
418 u32 savediv = 0, ratio, bestdiff = freq; fsl_sai_set_bclk() local
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/linux/drivers/gpu/drm/display/
H A Ddrm_scdc_helper.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
36 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
37 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
38 * HDMI source and HDMI sink to exchange data. The same I2C interface that
58 * drm_scdc_read - read a block of data from SCDC
64 * Reads a block of data from SCDC, starting at a given offset.
91 return -EPROTO; in drm_scdc_read()
98 * drm_scdc_write - write a block of data to SCDC
101 * @buffer: block of data to write
104 * Writes a block of data to SCDC, starting at a given offset.
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispresizer.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Resizer module
42 * "TRM ES3.1, table 12-46"
52 * Constants for ratio calculation
59 * 7-tap mode is for scale factors 0.25x to 0.5x.
60 * 4-tap mode is for scale factors 0.5x to 4.0x.
64 /* For 8-phase 4-tap horizontal filter: */
75 /* For 8-phase 4-tap vertical filter: */
86 /* For 4-phase 7-tap horizontal filter: */
94 /* For 4-phase 7-tap vertical filter: */
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/linux/sound/soc/codecs/
H A Dcs4270.c6 * Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed
15 * - Software mode is supported. Stand-alone mode is not supported.
16 * - Only I2C is supported, not SPI
17 * - Support for master and slave mode
18 * - The machine driver's 'startup' function must call
20 * - Only I2S and left-justified modes are supported
21 * - Power management is supported
51 #define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1)
101 /* Power-on default values for the registers
103 * This array contains the power-on default values of the registers, with the
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H A Dnau8325.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8325.c -- Nuvoton NAU8325 audio codec driver
25 /* Range of Master Clock MCLK (Hz) */
30 #define CLK_PROC_BYPASS (-1)
192 static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -8000, 600);
219 snd_soc_dapm_to_component(w->dapm); in nau8325_dac_event()
224 regmap_update_bits(nau8325->regmap, NAU8325_R12_MUTE_CTRL, in nau8325_dac_event()
230 regmap_update_bits(nau8325->regmap, NAU8325_R12_MUTE_CTRL, in nau8325_dac_event()
235 return -EINVAL; in nau8325_dac_event()
245 snd_soc_dapm_to_component(w->dapm); in nau8325_powerup_event()
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H A Des8316.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * es8316.c -- es8316 ALSA SoC audio driver
6 * Authors: David Yang <yangxiaohua@everest-semi.com>,
21 #include <sound/soc-dapm.h>
27 * MCLK/LRCK ratios, but we also add ratio 400, which is commonly used on
50 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9600, 50, 1);
51 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9600, 50, 1);
52 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_max_gain_tlv, -650, 150, 0);
53 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_min_gain_tlv, -1200, 150, 0);
56 0, 10, TLV_DB_SCALE_ITEM(-1650, 150, 0),
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H A Dnau8540.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <sound/soc-dapm.h>
50 /* ratio for input clk freq */
182 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
183 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in nau8540_fepga_event()
240 regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2, in nau8540_fepga_event()
256 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in nau8540_precharge_event()
261 regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE, in nau8540_precharge_event()
264 regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE, in nau8540_precharge_event()
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has many buses for data transfer between DRAM and
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
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/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
35 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
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/linux/Documentation/admin-guide/thermal/
H A Dintel_powerclamp.rst6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
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/linux/drivers/fpga/
H A Dsocfpga-a10.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Altera Corporation
10 #include <linux/fpga/fpga-mgr.h>
54 /* FPGA CD Ratio Value */
65 * struct a10_fpga_priv - private data for fpga manager
67 * @fpga_data_addr: iomap for single address data register to FPGA
68 * @clk: clock
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
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/linux/drivers/char/hw_random/
H A Dcctrng.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
23 #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
32 /* data circular buffer in words must be:
33 * - of a power-of-2 size (limitation of circ_buf.h macros)
34 * - at least 6, the size generated in the EHR according to HW implementation
41 * - SAMPLE_CNT is input value from the characterisation process
42 * - all the rest are constants
59 * Value of 0 indicates non-valid rosc
68 /* pending_hw - 1 when HW is pending, 0 when it is idle */
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/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
13 * these combinations is via the 'ratio's' which the clocks operate with
14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
16 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
19 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
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/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #include <media/media-device.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-ioctl.h>
30 #include <media/videobuf2-v4l2.h>
31 #include <media/videobuf2-dma-contig.h>
33 #include "camif-core.h"
36 /* HCLK CAMIF clock */
38 /* CAMIF / external camera sensor master clock */
94 * s3c_camif_find_format() - lookup camif color format by fourcc or an index
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/linux/drivers/ata/
H A Dpata_pdc2027x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
15 * as Documentation/driver-api/libata.rst
65 * ATA Timing Tables based on 133MHz controller clock.
66 * These tables are only used when the controller is in 133MHz clock.
67 * If the controller is in 100MHz clock, the ASIC hardware will
69 * is issued to the device. However, if the controller clock is 133MHz,
170 * port_mmio - Get the MMIO address of PDC2027x extended registers
176 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; in port_mmio()
180 * dev_mmio - Get the MMIO address of PDC2027x extended registers
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/linux/drivers/media/dvb-frontends/
H A Dcx24110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 cx24110 - Single Chip Satellite Channel Receiver driver module
5 Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
40 static struct {u8 reg; u8 data;} cx24110_regdata[]= member
50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
52 {0x0b,0x01}, /* set output clock in gapped mode, start signal low
54 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
74 /* leave front-end AGC parameters at default values */
82 {0x41,0x00}, /* @ MSB of front-end derotator frequency */
88 /* the cx24108 data sheet for symbol rates above 15MS/s */
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/linux/drivers/iio/adc/
H A Dsc27xx_adc.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/nvmem-consumer.h>
63 /* Timeout (us) for ADC data conversion according to ADC datasheet */
70 /* ADC voltage ratio definition */
101 * address and ratio, we should save ratio config and base
102 * in the device data structure.
111 void (*init_scale)(struct sc27xx_adc_data *data);
126 * should use the small-scale graph, and if more than 1.2v, we should use the
127 * big-scale graph.
161 return ((calib_data & 0xff) + calib_adc - 128) * 4; in sc27xx_adc_get_calib_data()
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/linux/drivers/clk/mvebu/
H A Dap-cpu-clk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell Armada AP CPU Clock Controller
11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt
13 #include <linux/clk-provider.h>
34 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
35 * @force_reg: request to force new ratio regardless of relation to other clocks
127 * struct ap806_clk: CPU cluster clock controller instance
128 * @cluster: Cluster clock controller index
129 * @clk_name: Cluster clock controller name
130 * @dev : Cluster clock device
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H A Dkirkwood.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
15 #include <linux/clk-provider.h>
24 * Kirkwood PLL sample-at-reset configuration
38 * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
44 * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
53 * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
172 /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */ in mv88f6180_get_clk_ratio()
218 * Clock Gating Control
242 * Clock Muxing Control
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/linux/drivers/devfreq/
H A Dexynos-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/devfreq-event.h>
38 unsigned int ratio; member
42 * Control the devfreq-event device to get the current state of bus
49 for (i = 0; i < bus->edev_count; i++) { \
50 if (!bus->edev[i]) \
52 ret = devfreq_event_##ops(bus->edev[i]); \
70 for (i = 0; i < bus->edev_count; i++) { in exynos_bus_get_event()
71 if (!bus->edev[i]) in exynos_bus_get_event()
74 ret = devfreq_event_get_event(bus->edev[i], &event_data); in exynos_bus_get_event()
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/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
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/linux/sound/soc/samsung/
H A Dspdif.c1 // SPDX-License-Identifier: GPL-2.0
3 // ALSA SoC Audio Layer - Samsung S/PDIF Controller driver
15 #include <linux/platform_data/asoc-s3c.h>
66 * struct samsung_spdif_info - Samsung S/PDIF Controller information
70 * @clk_rate: Current clock rate for calcurate ratio.
71 * @pclk: The peri-clock pointer for spdif master operation.
72 * @sclk: The source clock pointer for making sync signals.
107 void __iomem *regs = spdif->regs; in spdif_snd_txctrl()
110 dev_dbg(spdif->dev, "Entered %s\n", __func__); in spdif_snd_txctrl()
125 dev_dbg(spdif->dev, "Entered %s\n", __func__); in spdif_set_sysclk()
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/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * header file for Samsung EXYNOS5 SoC series G-Scaler driver
20 #include <media/videobuf2-v4l2.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/videobuf2-dma-contig.h>
27 #include "gsc-regs.h"
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