1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2c1644e3dSJohn Hsu /*
3c1644e3dSJohn Hsu * NAU85L40 ALSA SoC audio driver
4c1644e3dSJohn Hsu *
5c1644e3dSJohn Hsu * Copyright 2016 Nuvoton Technology Corp.
6c1644e3dSJohn Hsu * Author: John Hsu <KCHSU0@nuvoton.com>
7c1644e3dSJohn Hsu */
8c1644e3dSJohn Hsu
9c1644e3dSJohn Hsu #include <linux/module.h>
10c1644e3dSJohn Hsu #include <linux/moduleparam.h>
11c1644e3dSJohn Hsu #include <linux/init.h>
12c1644e3dSJohn Hsu #include <linux/delay.h>
13c1644e3dSJohn Hsu #include <linux/pm.h>
14c1644e3dSJohn Hsu #include <linux/i2c.h>
15c1644e3dSJohn Hsu #include <linux/regmap.h>
16c1644e3dSJohn Hsu #include <linux/regulator/consumer.h>
17c1644e3dSJohn Hsu #include <linux/spi/spi.h>
18c1644e3dSJohn Hsu #include <linux/slab.h>
19340d79a1SRob Herring #include <linux/of.h>
20c1644e3dSJohn Hsu #include <sound/core.h>
21c1644e3dSJohn Hsu #include <sound/pcm.h>
22c1644e3dSJohn Hsu #include <sound/pcm_params.h>
23c1644e3dSJohn Hsu #include <sound/soc.h>
24c1644e3dSJohn Hsu #include <sound/soc-dapm.h>
25c1644e3dSJohn Hsu #include <sound/initval.h>
26c1644e3dSJohn Hsu #include <sound/tlv.h>
27c1644e3dSJohn Hsu #include "nau8540.h"
28c1644e3dSJohn Hsu
29c1644e3dSJohn Hsu #define NAU_FREF_MAX 13500000
30c1644e3dSJohn Hsu #define NAU_FVCO_MAX 100000000
31c1644e3dSJohn Hsu #define NAU_FVCO_MIN 90000000
32c1644e3dSJohn Hsu
33c1644e3dSJohn Hsu /* the maximum frequency of CLK_ADC */
34c1644e3dSJohn Hsu #define CLK_ADC_MAX 6144000
35c1644e3dSJohn Hsu
36c1644e3dSJohn Hsu /* scaling for mclk from sysclk_src output */
37c1644e3dSJohn Hsu static const struct nau8540_fll_attr mclk_src_scaling[] = {
38c1644e3dSJohn Hsu { 1, 0x0 },
39c1644e3dSJohn Hsu { 2, 0x2 },
40c1644e3dSJohn Hsu { 4, 0x3 },
41c1644e3dSJohn Hsu { 8, 0x4 },
42c1644e3dSJohn Hsu { 16, 0x5 },
43c1644e3dSJohn Hsu { 32, 0x6 },
44c1644e3dSJohn Hsu { 3, 0x7 },
45c1644e3dSJohn Hsu { 6, 0xa },
46c1644e3dSJohn Hsu { 12, 0xb },
47c1644e3dSJohn Hsu { 24, 0xc },
48c1644e3dSJohn Hsu };
49c1644e3dSJohn Hsu
50c1644e3dSJohn Hsu /* ratio for input clk freq */
51c1644e3dSJohn Hsu static const struct nau8540_fll_attr fll_ratio[] = {
52c1644e3dSJohn Hsu { 512000, 0x01 },
53c1644e3dSJohn Hsu { 256000, 0x02 },
54c1644e3dSJohn Hsu { 128000, 0x04 },
55c1644e3dSJohn Hsu { 64000, 0x08 },
56c1644e3dSJohn Hsu { 32000, 0x10 },
57c1644e3dSJohn Hsu { 8000, 0x20 },
58c1644e3dSJohn Hsu { 4000, 0x40 },
59c1644e3dSJohn Hsu };
60c1644e3dSJohn Hsu
61c1644e3dSJohn Hsu static const struct nau8540_fll_attr fll_pre_scalar[] = {
62c1644e3dSJohn Hsu { 1, 0x0 },
63c1644e3dSJohn Hsu { 2, 0x1 },
64c1644e3dSJohn Hsu { 4, 0x2 },
65c1644e3dSJohn Hsu { 8, 0x3 },
66c1644e3dSJohn Hsu };
67c1644e3dSJohn Hsu
68c1644e3dSJohn Hsu /* over sampling rate */
69c1644e3dSJohn Hsu static const struct nau8540_osr_attr osr_adc_sel[] = {
70c1644e3dSJohn Hsu { 32, 3 }, /* OSR 32, SRC 1/8 */
71c1644e3dSJohn Hsu { 64, 2 }, /* OSR 64, SRC 1/4 */
72c1644e3dSJohn Hsu { 128, 1 }, /* OSR 128, SRC 1/2 */
73c1644e3dSJohn Hsu { 256, 0 }, /* OSR 256, SRC 1 */
74c1644e3dSJohn Hsu };
75c1644e3dSJohn Hsu
76c1644e3dSJohn Hsu static const struct reg_default nau8540_reg_defaults[] = {
77c1644e3dSJohn Hsu {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
78c1644e3dSJohn Hsu {NAU8540_REG_CLOCK_CTRL, 0x0000},
79c1644e3dSJohn Hsu {NAU8540_REG_CLOCK_SRC, 0x0000},
80c1644e3dSJohn Hsu {NAU8540_REG_FLL1, 0x0001},
81c1644e3dSJohn Hsu {NAU8540_REG_FLL2, 0x3126},
82c1644e3dSJohn Hsu {NAU8540_REG_FLL3, 0x0008},
83c1644e3dSJohn Hsu {NAU8540_REG_FLL4, 0x0010},
84c1644e3dSJohn Hsu {NAU8540_REG_FLL5, 0xC000},
85c1644e3dSJohn Hsu {NAU8540_REG_FLL6, 0x6000},
86c1644e3dSJohn Hsu {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
87c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL0, 0x000B},
88c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL1, 0x3010},
89c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL2, 0x0800},
90c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL3, 0x0000},
91c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL4, 0x000F},
92c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_1, 0x0000},
93c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_2, 0x700B},
94c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_3, 0x0022},
95c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_4, 0x1010},
96c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_5, 0x1010},
97c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
98c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
99c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
100c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
101c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
102c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
103c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
104c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
105c1644e3dSJohn Hsu {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
106c1644e3dSJohn Hsu {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
107c1644e3dSJohn Hsu {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
108c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
109c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
110c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
111c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
112c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_MUX, 0x00E4},
113c1644e3dSJohn Hsu {NAU8540_REG_GPIO_CTRL, 0x0000},
114c1644e3dSJohn Hsu {NAU8540_REG_MISC_CTRL, 0x0000},
115c1644e3dSJohn Hsu {NAU8540_REG_I2C_CTRL, 0xEFFF},
116c1644e3dSJohn Hsu {NAU8540_REG_VMID_CTRL, 0x0000},
117c1644e3dSJohn Hsu {NAU8540_REG_MUTE, 0x0000},
118c1644e3dSJohn Hsu {NAU8540_REG_ANALOG_ADC1, 0x0011},
119c1644e3dSJohn Hsu {NAU8540_REG_ANALOG_ADC2, 0x0020},
120c1644e3dSJohn Hsu {NAU8540_REG_ANALOG_PWR, 0x0000},
121c1644e3dSJohn Hsu {NAU8540_REG_MIC_BIAS, 0x0004},
122c1644e3dSJohn Hsu {NAU8540_REG_REFERENCE, 0x0000},
123c1644e3dSJohn Hsu {NAU8540_REG_FEPGA1, 0x0000},
124c1644e3dSJohn Hsu {NAU8540_REG_FEPGA2, 0x0000},
125c1644e3dSJohn Hsu {NAU8540_REG_FEPGA3, 0x0101},
126c1644e3dSJohn Hsu {NAU8540_REG_FEPGA4, 0x0101},
127c1644e3dSJohn Hsu {NAU8540_REG_PWR, 0x0000},
128c1644e3dSJohn Hsu };
129c1644e3dSJohn Hsu
nau8540_readable_reg(struct device * dev,unsigned int reg)130c1644e3dSJohn Hsu static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
131c1644e3dSJohn Hsu {
132c1644e3dSJohn Hsu switch (reg) {
133c1644e3dSJohn Hsu case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
134c1644e3dSJohn Hsu case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
135c1644e3dSJohn Hsu case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
136c1644e3dSJohn Hsu case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
137c1644e3dSJohn Hsu case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
138c1644e3dSJohn Hsu case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
139c1644e3dSJohn Hsu case NAU8540_REG_I2C_DEVICE_ID:
140c1644e3dSJohn Hsu case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
141c1644e3dSJohn Hsu case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
142c1644e3dSJohn Hsu return true;
143c1644e3dSJohn Hsu default:
144c1644e3dSJohn Hsu return false;
145c1644e3dSJohn Hsu }
146c1644e3dSJohn Hsu
147c1644e3dSJohn Hsu }
148c1644e3dSJohn Hsu
nau8540_writeable_reg(struct device * dev,unsigned int reg)149c1644e3dSJohn Hsu static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
150c1644e3dSJohn Hsu {
151c1644e3dSJohn Hsu switch (reg) {
152c1644e3dSJohn Hsu case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
153c1644e3dSJohn Hsu case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
154c1644e3dSJohn Hsu case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
155c1644e3dSJohn Hsu case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
156c1644e3dSJohn Hsu case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
157c1644e3dSJohn Hsu case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
158c1644e3dSJohn Hsu case NAU8540_REG_RST:
159c1644e3dSJohn Hsu case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
160c1644e3dSJohn Hsu case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
161c1644e3dSJohn Hsu return true;
162c1644e3dSJohn Hsu default:
163c1644e3dSJohn Hsu return false;
164c1644e3dSJohn Hsu }
165c1644e3dSJohn Hsu }
166c1644e3dSJohn Hsu
nau8540_volatile_reg(struct device * dev,unsigned int reg)167c1644e3dSJohn Hsu static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
168c1644e3dSJohn Hsu {
169c1644e3dSJohn Hsu switch (reg) {
170c1644e3dSJohn Hsu case NAU8540_REG_SW_RESET:
171c1644e3dSJohn Hsu case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
172c1644e3dSJohn Hsu case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
173c1644e3dSJohn Hsu case NAU8540_REG_I2C_DEVICE_ID:
174c1644e3dSJohn Hsu case NAU8540_REG_RST:
175c1644e3dSJohn Hsu return true;
176c1644e3dSJohn Hsu default:
177c1644e3dSJohn Hsu return false;
178c1644e3dSJohn Hsu }
179c1644e3dSJohn Hsu }
180c1644e3dSJohn Hsu
181c1644e3dSJohn Hsu
182c1644e3dSJohn Hsu static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
183c1644e3dSJohn Hsu static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
184c1644e3dSJohn Hsu
185c1644e3dSJohn Hsu static const struct snd_kcontrol_new nau8540_snd_controls[] = {
186c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
187c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv),
188c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
189c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv),
190c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
191c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv),
192c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
193c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv),
194c1644e3dSJohn Hsu
195c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
196c1644e3dSJohn Hsu 0, 0x25, 0, fepga_gain_tlv),
197c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
198c1644e3dSJohn Hsu 8, 0x25, 0, fepga_gain_tlv),
199c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
200c1644e3dSJohn Hsu 0, 0x25, 0, fepga_gain_tlv),
201c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
202c1644e3dSJohn Hsu 8, 0x25, 0, fepga_gain_tlv),
203c1644e3dSJohn Hsu };
204c1644e3dSJohn Hsu
205c1644e3dSJohn Hsu static const char * const adc_channel[] = {
206c1644e3dSJohn Hsu "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
207c1644e3dSJohn Hsu };
208c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL(
209c1644e3dSJohn Hsu digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
210c1644e3dSJohn Hsu
211c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch4_mux =
212c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
213c1644e3dSJohn Hsu
214c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL(
215c1644e3dSJohn Hsu digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
216c1644e3dSJohn Hsu
217c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch3_mux =
218c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
219c1644e3dSJohn Hsu
220c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL(
221c1644e3dSJohn Hsu digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
222c1644e3dSJohn Hsu
223c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch2_mux =
224c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
225c1644e3dSJohn Hsu
226c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL(
227c1644e3dSJohn Hsu digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
228c1644e3dSJohn Hsu
229c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch1_mux =
230c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
231c1644e3dSJohn Hsu
nau8540_fepga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)2329423d7b9SDavid Lin static int nau8540_fepga_event(struct snd_soc_dapm_widget *w,
2339423d7b9SDavid Lin struct snd_kcontrol *k, int event)
2349423d7b9SDavid Lin {
2359423d7b9SDavid Lin struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2369423d7b9SDavid Lin struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
2379423d7b9SDavid Lin
2389423d7b9SDavid Lin switch (event) {
2399423d7b9SDavid Lin case SND_SOC_DAPM_POST_PMU:
2409423d7b9SDavid Lin regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,
2419423d7b9SDavid Lin NAU8540_ACDC_CTL_MASK, NAU8540_ACDC_CTL_MIC1P_VREF |
2429423d7b9SDavid Lin NAU8540_ACDC_CTL_MIC1N_VREF | NAU8540_ACDC_CTL_MIC2P_VREF |
2439423d7b9SDavid Lin NAU8540_ACDC_CTL_MIC2N_VREF | NAU8540_ACDC_CTL_MIC3P_VREF |
2449423d7b9SDavid Lin NAU8540_ACDC_CTL_MIC3N_VREF | NAU8540_ACDC_CTL_MIC4P_VREF |
2459423d7b9SDavid Lin NAU8540_ACDC_CTL_MIC4N_VREF);
2469423d7b9SDavid Lin break;
2479423d7b9SDavid Lin default:
2489423d7b9SDavid Lin break;
2499423d7b9SDavid Lin }
2509423d7b9SDavid Lin return 0;
2519423d7b9SDavid Lin }
2529423d7b9SDavid Lin
nau8540_precharge_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)2539423d7b9SDavid Lin static int nau8540_precharge_event(struct snd_soc_dapm_widget *w,
2549423d7b9SDavid Lin struct snd_kcontrol *k, int event)
2559423d7b9SDavid Lin {
2569423d7b9SDavid Lin struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2579423d7b9SDavid Lin struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
2589423d7b9SDavid Lin
2599423d7b9SDavid Lin switch (event) {
2609423d7b9SDavid Lin case SND_SOC_DAPM_POST_PMU:
2619423d7b9SDavid Lin regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,
2629423d7b9SDavid Lin NAU8540_DISCHRG_EN, NAU8540_DISCHRG_EN);
2639423d7b9SDavid Lin msleep(40);
2649423d7b9SDavid Lin regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,
2659423d7b9SDavid Lin NAU8540_DISCHRG_EN, 0);
2669423d7b9SDavid Lin regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,
2679423d7b9SDavid Lin NAU8540_ACDC_CTL_MASK, 0);
2689423d7b9SDavid Lin break;
2699423d7b9SDavid Lin default:
2709423d7b9SDavid Lin break;
2719423d7b9SDavid Lin }
2729423d7b9SDavid Lin return 0;
2739423d7b9SDavid Lin }
2749423d7b9SDavid Lin
adc_power_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)2756573c051SJohn Hsu static int adc_power_control(struct snd_soc_dapm_widget *w,
2766573c051SJohn Hsu struct snd_kcontrol *k, int event)
2776573c051SJohn Hsu {
278415bc3a0SKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
279415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
2806573c051SJohn Hsu
2816573c051SJohn Hsu if (SND_SOC_DAPM_EVENT_ON(event)) {
2829423d7b9SDavid Lin msleep(160);
2836573c051SJohn Hsu /* DO12 and DO34 pad output enable */
2849423d7b9SDavid Lin regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
2859423d7b9SDavid Lin NAU8540_ADC_ALL_EN, NAU8540_ADC_ALL_EN);
2866573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
2876573c051SJohn Hsu NAU8540_I2S_DO12_TRI, 0);
2886573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
2896573c051SJohn Hsu NAU8540_I2S_DO34_TRI, 0);
2906573c051SJohn Hsu } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
2916573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
2926573c051SJohn Hsu NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
2936573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
2946573c051SJohn Hsu NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
2959423d7b9SDavid Lin regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
2969423d7b9SDavid Lin NAU8540_ADC_ALL_EN, 0);
2976573c051SJohn Hsu }
2986573c051SJohn Hsu return 0;
2996573c051SJohn Hsu }
3006573c051SJohn Hsu
aiftx_power_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)301e4d0db60SJohn Hsu static int aiftx_power_control(struct snd_soc_dapm_widget *w,
302e4d0db60SJohn Hsu struct snd_kcontrol *k, int event)
303e4d0db60SJohn Hsu {
304415bc3a0SKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
305415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
306e4d0db60SJohn Hsu
307e4d0db60SJohn Hsu if (SND_SOC_DAPM_EVENT_OFF(event)) {
308e4d0db60SJohn Hsu regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
309e4d0db60SJohn Hsu regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
310e4d0db60SJohn Hsu }
311e4d0db60SJohn Hsu return 0;
312e4d0db60SJohn Hsu }
313e4d0db60SJohn Hsu
314c1644e3dSJohn Hsu static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
315c1644e3dSJohn Hsu SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
316c1644e3dSJohn Hsu SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
317c1644e3dSJohn Hsu
318c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC1"),
319c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC2"),
320c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC3"),
321c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC4"),
322c1644e3dSJohn Hsu
3239423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("Frontend PGA1", 0, NAU8540_REG_PWR, 12, 0,
3249423d7b9SDavid Lin nau8540_fepga_event, SND_SOC_DAPM_POST_PMU),
3259423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("Frontend PGA2", 0, NAU8540_REG_PWR, 13, 0,
3269423d7b9SDavid Lin nau8540_fepga_event, SND_SOC_DAPM_POST_PMU),
3279423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("Frontend PGA3", 0, NAU8540_REG_PWR, 14, 0,
3289423d7b9SDavid Lin nau8540_fepga_event, SND_SOC_DAPM_POST_PMU),
3299423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("Frontend PGA4", 0, NAU8540_REG_PWR, 15, 0,
3309423d7b9SDavid Lin nau8540_fepga_event, SND_SOC_DAPM_POST_PMU),
331c1644e3dSJohn Hsu
3329423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("Precharge", 1, SND_SOC_NOPM, 0, 0,
3339423d7b9SDavid Lin nau8540_precharge_event, SND_SOC_DAPM_POST_PMU),
334c1644e3dSJohn Hsu
3359423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("ADC CH1", 2, NAU8540_REG_ANALOG_PWR, 0, 0,
3369423d7b9SDavid Lin adc_power_control, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3379423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("ADC CH2", 2, NAU8540_REG_ANALOG_PWR, 1, 0,
3389423d7b9SDavid Lin adc_power_control, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3399423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("ADC CH3", 2, NAU8540_REG_ANALOG_PWR, 2, 0,
3409423d7b9SDavid Lin adc_power_control, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3419423d7b9SDavid Lin SND_SOC_DAPM_PGA_S("ADC CH4", 2, NAU8540_REG_ANALOG_PWR, 3, 0,
3429423d7b9SDavid Lin adc_power_control, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
343c1644e3dSJohn Hsu
344c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH4 Mux",
345c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
346c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH3 Mux",
347c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
348c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH2 Mux",
349c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
350c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH1 Mux",
351c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
352c1644e3dSJohn Hsu
353e4d0db60SJohn Hsu SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
354e4d0db60SJohn Hsu aiftx_power_control, SND_SOC_DAPM_POST_PMD),
355c1644e3dSJohn Hsu };
356c1644e3dSJohn Hsu
357c1644e3dSJohn Hsu static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
358c1644e3dSJohn Hsu {"Frontend PGA1", NULL, "MIC1"},
359c1644e3dSJohn Hsu {"Frontend PGA2", NULL, "MIC2"},
360c1644e3dSJohn Hsu {"Frontend PGA3", NULL, "MIC3"},
361c1644e3dSJohn Hsu {"Frontend PGA4", NULL, "MIC4"},
362c1644e3dSJohn Hsu
3639423d7b9SDavid Lin {"Precharge", NULL, "Frontend PGA1"},
3649423d7b9SDavid Lin {"Precharge", NULL, "Frontend PGA2"},
3659423d7b9SDavid Lin {"Precharge", NULL, "Frontend PGA3"},
3669423d7b9SDavid Lin {"Precharge", NULL, "Frontend PGA4"},
367c1644e3dSJohn Hsu
3689423d7b9SDavid Lin {"ADC CH1", NULL, "Precharge"},
3699423d7b9SDavid Lin {"ADC CH2", NULL, "Precharge"},
3709423d7b9SDavid Lin {"ADC CH3", NULL, "Precharge"},
3719423d7b9SDavid Lin {"ADC CH4", NULL, "Precharge"},
372c1644e3dSJohn Hsu
3739423d7b9SDavid Lin {"ADC CH1", NULL, "MICBIAS1"},
3749423d7b9SDavid Lin {"ADC CH2", NULL, "MICBIAS1"},
3759423d7b9SDavid Lin {"ADC CH3", NULL, "MICBIAS2"},
3769423d7b9SDavid Lin {"ADC CH4", NULL, "MICBIAS2"},
377c1644e3dSJohn Hsu
378c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
379c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
380c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
381c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
382c1644e3dSJohn Hsu
383c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
384c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
385c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
386c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
387c1644e3dSJohn Hsu
388c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
389c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
390c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
391c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
392c1644e3dSJohn Hsu
393c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
394c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
395c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
396c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
397c1644e3dSJohn Hsu
398c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH1 Mux"},
399c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH2 Mux"},
400c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH3 Mux"},
401c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH4 Mux"},
402c1644e3dSJohn Hsu };
403c1644e3dSJohn Hsu
404be919239STakashi Iwai static const struct nau8540_osr_attr *
nau8540_get_osr(struct nau8540 * nau8540)405be919239STakashi Iwai nau8540_get_osr(struct nau8540 *nau8540)
406c1644e3dSJohn Hsu {
407be919239STakashi Iwai unsigned int osr;
408c1644e3dSJohn Hsu
409be919239STakashi Iwai regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
410be919239STakashi Iwai osr &= NAU8540_ADC_OSR_MASK;
411be919239STakashi Iwai if (osr >= ARRAY_SIZE(osr_adc_sel))
412be919239STakashi Iwai return NULL;
413be919239STakashi Iwai return &osr_adc_sel[osr];
414c1644e3dSJohn Hsu }
415c1644e3dSJohn Hsu
nau8540_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)416be919239STakashi Iwai static int nau8540_dai_startup(struct snd_pcm_substream *substream,
417be919239STakashi Iwai struct snd_soc_dai *dai)
418be919239STakashi Iwai {
419be919239STakashi Iwai struct snd_soc_component *component = dai->component;
420be919239STakashi Iwai struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
421be919239STakashi Iwai const struct nau8540_osr_attr *osr;
422be919239STakashi Iwai
423be919239STakashi Iwai osr = nau8540_get_osr(nau8540);
424be919239STakashi Iwai if (!osr || !osr->osr)
425be919239STakashi Iwai return -EINVAL;
426be919239STakashi Iwai
427be919239STakashi Iwai return snd_pcm_hw_constraint_minmax(substream->runtime,
428be919239STakashi Iwai SNDRV_PCM_HW_PARAM_RATE,
429be919239STakashi Iwai 0, CLK_ADC_MAX / osr->osr);
430c1644e3dSJohn Hsu }
431c1644e3dSJohn Hsu
nau8540_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)432c1644e3dSJohn Hsu static int nau8540_hw_params(struct snd_pcm_substream *substream,
433c1644e3dSJohn Hsu struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
434c1644e3dSJohn Hsu {
435415bc3a0SKuninori Morimoto struct snd_soc_component *component = dai->component;
436415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
437be919239STakashi Iwai unsigned int val_len = 0;
438be919239STakashi Iwai const struct nau8540_osr_attr *osr;
439c1644e3dSJohn Hsu
440c1644e3dSJohn Hsu /* CLK_ADC = OSR * FS
441c1644e3dSJohn Hsu * ADC clock frequency is defined as Over Sampling Rate (OSR)
442c1644e3dSJohn Hsu * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
443c1644e3dSJohn Hsu * values must be selected such that the maximum frequency is less
444c1644e3dSJohn Hsu * than 6.144 MHz.
445c1644e3dSJohn Hsu */
446be919239STakashi Iwai osr = nau8540_get_osr(nau8540);
447be919239STakashi Iwai if (!osr || !osr->osr)
448be919239STakashi Iwai return -EINVAL;
449be919239STakashi Iwai if (params_rate(params) * osr->osr > CLK_ADC_MAX)
450c1644e3dSJohn Hsu return -EINVAL;
451c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
452c1644e3dSJohn Hsu NAU8540_CLK_ADC_SRC_MASK,
453be919239STakashi Iwai osr->clk_src << NAU8540_CLK_ADC_SRC_SFT);
454c1644e3dSJohn Hsu
455c1644e3dSJohn Hsu switch (params_width(params)) {
456c1644e3dSJohn Hsu case 16:
457c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_16;
458c1644e3dSJohn Hsu break;
459c1644e3dSJohn Hsu case 20:
460c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_20;
461c1644e3dSJohn Hsu break;
462c1644e3dSJohn Hsu case 24:
463c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_24;
464c1644e3dSJohn Hsu break;
465c1644e3dSJohn Hsu case 32:
466c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_32;
467c1644e3dSJohn Hsu break;
468c1644e3dSJohn Hsu default:
469c1644e3dSJohn Hsu return -EINVAL;
470c1644e3dSJohn Hsu }
471c1644e3dSJohn Hsu
472c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
473c1644e3dSJohn Hsu NAU8540_I2S_DL_MASK, val_len);
474c1644e3dSJohn Hsu
475c1644e3dSJohn Hsu return 0;
476c1644e3dSJohn Hsu }
477c1644e3dSJohn Hsu
nau8540_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)478c1644e3dSJohn Hsu static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
479c1644e3dSJohn Hsu {
480415bc3a0SKuninori Morimoto struct snd_soc_component *component = dai->component;
481415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
482c1644e3dSJohn Hsu unsigned int ctrl1_val = 0, ctrl2_val = 0;
483c1644e3dSJohn Hsu
484c1644e3dSJohn Hsu switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
485c1644e3dSJohn Hsu case SND_SOC_DAIFMT_CBM_CFM:
486c1644e3dSJohn Hsu ctrl2_val |= NAU8540_I2S_MS_MASTER;
487c1644e3dSJohn Hsu break;
488c1644e3dSJohn Hsu case SND_SOC_DAIFMT_CBS_CFS:
489c1644e3dSJohn Hsu break;
490c1644e3dSJohn Hsu default:
491c1644e3dSJohn Hsu return -EINVAL;
492c1644e3dSJohn Hsu }
493c1644e3dSJohn Hsu
494c1644e3dSJohn Hsu switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
495c1644e3dSJohn Hsu case SND_SOC_DAIFMT_NB_NF:
496c1644e3dSJohn Hsu break;
497c1644e3dSJohn Hsu case SND_SOC_DAIFMT_IB_NF:
498c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_BP_INV;
499c1644e3dSJohn Hsu break;
500c1644e3dSJohn Hsu default:
501c1644e3dSJohn Hsu return -EINVAL;
502c1644e3dSJohn Hsu }
503c1644e3dSJohn Hsu
504c1644e3dSJohn Hsu switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
505c1644e3dSJohn Hsu case SND_SOC_DAIFMT_I2S:
506c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_I2S;
507c1644e3dSJohn Hsu break;
508c1644e3dSJohn Hsu case SND_SOC_DAIFMT_LEFT_J:
509c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_LEFT;
510c1644e3dSJohn Hsu break;
511c1644e3dSJohn Hsu case SND_SOC_DAIFMT_RIGHT_J:
512c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_RIGTH;
513c1644e3dSJohn Hsu break;
514c1644e3dSJohn Hsu case SND_SOC_DAIFMT_DSP_A:
515c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
516c1644e3dSJohn Hsu break;
517c1644e3dSJohn Hsu case SND_SOC_DAIFMT_DSP_B:
518c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
519c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_PCMB_EN;
520c1644e3dSJohn Hsu break;
521c1644e3dSJohn Hsu default:
522c1644e3dSJohn Hsu return -EINVAL;
523c1644e3dSJohn Hsu }
524c1644e3dSJohn Hsu
525c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
526c1644e3dSJohn Hsu NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
527c1644e3dSJohn Hsu NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
528c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
529c1644e3dSJohn Hsu NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
530c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
531c1644e3dSJohn Hsu NAU8540_I2S_DO34_OE, 0);
532c1644e3dSJohn Hsu
533c1644e3dSJohn Hsu return 0;
534c1644e3dSJohn Hsu }
535c1644e3dSJohn Hsu
536c1644e3dSJohn Hsu /**
537c1644e3dSJohn Hsu * nau8540_set_tdm_slot - configure DAI TX TDM.
538c1644e3dSJohn Hsu * @dai: DAI
539c1644e3dSJohn Hsu * @tx_mask: bitmask representing active TX slots. Ex.
540c1644e3dSJohn Hsu * 0xf for normal 4 channel TDM.
541c1644e3dSJohn Hsu * 0xf0 for shifted 4 channel TDM
542c1644e3dSJohn Hsu * @rx_mask: no used.
543c1644e3dSJohn Hsu * @slots: Number of slots in use.
544c1644e3dSJohn Hsu * @slot_width: Width in bits for each slot.
545c1644e3dSJohn Hsu *
546c1644e3dSJohn Hsu * Configures a DAI for TDM operation. Only support 4 slots TDM.
547c1644e3dSJohn Hsu */
nau8540_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)548c1644e3dSJohn Hsu static int nau8540_set_tdm_slot(struct snd_soc_dai *dai,
549c1644e3dSJohn Hsu unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
550c1644e3dSJohn Hsu {
551415bc3a0SKuninori Morimoto struct snd_soc_component *component = dai->component;
552415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
553c1644e3dSJohn Hsu unsigned int ctrl2_val = 0, ctrl4_val = 0;
554c1644e3dSJohn Hsu
555c1644e3dSJohn Hsu if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
556c1644e3dSJohn Hsu return -EINVAL;
557c1644e3dSJohn Hsu
558c1644e3dSJohn Hsu ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
559c1644e3dSJohn Hsu if (tx_mask & 0xf0) {
560c1644e3dSJohn Hsu ctrl2_val = 4 * slot_width;
561c1644e3dSJohn Hsu ctrl4_val |= (tx_mask >> 4);
562c1644e3dSJohn Hsu } else {
563c1644e3dSJohn Hsu ctrl4_val |= tx_mask;
564c1644e3dSJohn Hsu }
565c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
566c1644e3dSJohn Hsu NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
567c1644e3dSJohn Hsu NAU8540_TDM_TX_MASK, ctrl4_val);
568c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
569c1644e3dSJohn Hsu NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
570c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
571c1644e3dSJohn Hsu NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
572c1644e3dSJohn Hsu NAU8540_I2S_DO34_OE | ctrl2_val);
573c1644e3dSJohn Hsu
574c1644e3dSJohn Hsu return 0;
575c1644e3dSJohn Hsu }
576c1644e3dSJohn Hsu
nau8540_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)577a60a609bSDavid Lin static int nau8540_dai_trigger(struct snd_pcm_substream *substream,
578a60a609bSDavid Lin int cmd, struct snd_soc_dai *dai)
579a60a609bSDavid Lin {
580a60a609bSDavid Lin struct snd_soc_component *component = dai->component;
581a60a609bSDavid Lin struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
582a60a609bSDavid Lin struct regmap *regmap = nau8540->regmap;
583a60a609bSDavid Lin unsigned int val;
584a60a609bSDavid Lin int ret = 0;
585a60a609bSDavid Lin
586a60a609bSDavid Lin /* Reading the peak data to detect abnormal data in the ADC channel.
587a60a609bSDavid Lin * If abnormal data happens, the driver takes recovery actions to
588a60a609bSDavid Lin * refresh the ADC channel.
589a60a609bSDavid Lin */
590a60a609bSDavid Lin switch (cmd) {
591a60a609bSDavid Lin case SNDRV_PCM_TRIGGER_START:
592a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
593a60a609bSDavid Lin NAU8540_CLK_AGC_EN, NAU8540_CLK_AGC_EN);
594a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_ALC_CONTROL_3,
595a60a609bSDavid Lin NAU8540_ALC_CH_ALL_EN, NAU8540_ALC_CH_ALL_EN);
596a60a609bSDavid Lin
597a60a609bSDavid Lin regmap_read(regmap, NAU8540_REG_PEAK_CH1, &val);
598a60a609bSDavid Lin dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val);
599a60a609bSDavid Lin if (!val) {
600a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_MUTE,
601a60a609bSDavid Lin NAU8540_PGA_CH_ALL_MUTE, NAU8540_PGA_CH_ALL_MUTE);
602a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_MUTE,
603a60a609bSDavid Lin NAU8540_PGA_CH_ALL_MUTE, 0);
604a60a609bSDavid Lin regmap_write(regmap, NAU8540_REG_RST, 0x1);
605a60a609bSDavid Lin regmap_write(regmap, NAU8540_REG_RST, 0);
606a60a609bSDavid Lin regmap_read(regmap, NAU8540_REG_PEAK_CH1, &val);
607a60a609bSDavid Lin dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val);
608a60a609bSDavid Lin if (!val) {
609a60a609bSDavid Lin dev_err(nau8540->dev, "Channel recovery failed!!");
610a60a609bSDavid Lin ret = -EIO;
611a60a609bSDavid Lin }
612a60a609bSDavid Lin }
613a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
614a60a609bSDavid Lin NAU8540_CLK_AGC_EN, 0);
615a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_ALC_CONTROL_3,
616a60a609bSDavid Lin NAU8540_ALC_CH_ALL_EN, 0);
617a60a609bSDavid Lin break;
618a60a609bSDavid Lin
619a60a609bSDavid Lin default:
620a60a609bSDavid Lin break;
621a60a609bSDavid Lin }
622a60a609bSDavid Lin
623a60a609bSDavid Lin return ret;
624a60a609bSDavid Lin }
625c1644e3dSJohn Hsu
626c1644e3dSJohn Hsu static const struct snd_soc_dai_ops nau8540_dai_ops = {
627be919239STakashi Iwai .startup = nau8540_dai_startup,
628c1644e3dSJohn Hsu .hw_params = nau8540_hw_params,
629c1644e3dSJohn Hsu .set_fmt = nau8540_set_fmt,
630c1644e3dSJohn Hsu .set_tdm_slot = nau8540_set_tdm_slot,
631a60a609bSDavid Lin .trigger = nau8540_dai_trigger,
632c1644e3dSJohn Hsu };
633c1644e3dSJohn Hsu
634c1644e3dSJohn Hsu #define NAU8540_RATES SNDRV_PCM_RATE_8000_48000
635c1644e3dSJohn Hsu #define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
636c1644e3dSJohn Hsu | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
637c1644e3dSJohn Hsu
638c1644e3dSJohn Hsu static struct snd_soc_dai_driver nau8540_dai = {
639c1644e3dSJohn Hsu .name = "nau8540-hifi",
640c1644e3dSJohn Hsu .capture = {
641c1644e3dSJohn Hsu .stream_name = "Capture",
642c1644e3dSJohn Hsu .channels_min = 1,
643c1644e3dSJohn Hsu .channels_max = 4,
644c1644e3dSJohn Hsu .rates = NAU8540_RATES,
645c1644e3dSJohn Hsu .formats = NAU8540_FORMATS,
646c1644e3dSJohn Hsu },
647c1644e3dSJohn Hsu .ops = &nau8540_dai_ops,
648c1644e3dSJohn Hsu };
649c1644e3dSJohn Hsu
650c1644e3dSJohn Hsu /**
651c1644e3dSJohn Hsu * nau8540_calc_fll_param - Calculate FLL parameters.
652c1644e3dSJohn Hsu * @fll_in: external clock provided to codec.
653c1644e3dSJohn Hsu * @fs: sampling rate.
654c1644e3dSJohn Hsu * @fll_param: Pointer to structure of FLL parameters.
655c1644e3dSJohn Hsu *
656c1644e3dSJohn Hsu * Calculate FLL parameters to configure codec.
657c1644e3dSJohn Hsu *
658c1644e3dSJohn Hsu * Returns 0 for success or negative error code.
659c1644e3dSJohn Hsu */
nau8540_calc_fll_param(unsigned int fll_in,unsigned int fs,struct nau8540_fll * fll_param)660c1644e3dSJohn Hsu static int nau8540_calc_fll_param(unsigned int fll_in,
661c1644e3dSJohn Hsu unsigned int fs, struct nau8540_fll *fll_param)
662c1644e3dSJohn Hsu {
663c1644e3dSJohn Hsu u64 fvco, fvco_max;
664c1644e3dSJohn Hsu unsigned int fref, i, fvco_sel;
665c1644e3dSJohn Hsu
666c1644e3dSJohn Hsu /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
667c1644e3dSJohn Hsu * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
668c1644e3dSJohn Hsu * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
669c1644e3dSJohn Hsu */
670c1644e3dSJohn Hsu for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
671c1644e3dSJohn Hsu fref = fll_in / fll_pre_scalar[i].param;
672c1644e3dSJohn Hsu if (fref <= NAU_FREF_MAX)
673c1644e3dSJohn Hsu break;
674c1644e3dSJohn Hsu }
675c1644e3dSJohn Hsu if (i == ARRAY_SIZE(fll_pre_scalar))
676c1644e3dSJohn Hsu return -EINVAL;
677c1644e3dSJohn Hsu fll_param->clk_ref_div = fll_pre_scalar[i].val;
678c1644e3dSJohn Hsu
679c1644e3dSJohn Hsu /* Choose the FLL ratio based on FREF */
680c1644e3dSJohn Hsu for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
681c1644e3dSJohn Hsu if (fref >= fll_ratio[i].param)
682c1644e3dSJohn Hsu break;
683c1644e3dSJohn Hsu }
684c1644e3dSJohn Hsu if (i == ARRAY_SIZE(fll_ratio))
685c1644e3dSJohn Hsu return -EINVAL;
686c1644e3dSJohn Hsu fll_param->ratio = fll_ratio[i].val;
687c1644e3dSJohn Hsu
688c1644e3dSJohn Hsu /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
689c1644e3dSJohn Hsu * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
690c1644e3dSJohn Hsu * guaranteed across the full range of operation.
691c1644e3dSJohn Hsu * FDCO = freq_out * 2 * mclk_src_scaling
692c1644e3dSJohn Hsu */
693c1644e3dSJohn Hsu fvco_max = 0;
694c1644e3dSJohn Hsu fvco_sel = ARRAY_SIZE(mclk_src_scaling);
695c1644e3dSJohn Hsu for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
696cd7fdc45SYoung_X fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
697c1644e3dSJohn Hsu if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
698c1644e3dSJohn Hsu fvco_max < fvco) {
699c1644e3dSJohn Hsu fvco_max = fvco;
700c1644e3dSJohn Hsu fvco_sel = i;
701c1644e3dSJohn Hsu }
702c1644e3dSJohn Hsu }
703c1644e3dSJohn Hsu if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
704c1644e3dSJohn Hsu return -EINVAL;
705c1644e3dSJohn Hsu fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
706c1644e3dSJohn Hsu
707c1644e3dSJohn Hsu /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
708c1644e3dSJohn Hsu * input based on FDCO, FREF and FLL ratio.
709c1644e3dSJohn Hsu */
710c1644e3dSJohn Hsu fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
711c1644e3dSJohn Hsu fll_param->fll_int = (fvco >> 16) & 0x3FF;
712c1644e3dSJohn Hsu fll_param->fll_frac = fvco & 0xFFFF;
713c1644e3dSJohn Hsu return 0;
714c1644e3dSJohn Hsu }
715c1644e3dSJohn Hsu
nau8540_fll_apply(struct regmap * regmap,struct nau8540_fll * fll_param)716c1644e3dSJohn Hsu static void nau8540_fll_apply(struct regmap *regmap,
717c1644e3dSJohn Hsu struct nau8540_fll *fll_param)
718c1644e3dSJohn Hsu {
719c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
720c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
721c1644e3dSJohn Hsu NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
722c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL1,
723fe83b1b7SJohn Hsu NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
724fe83b1b7SJohn Hsu fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
725c1644e3dSJohn Hsu /* FLL 16-bit fractional input */
726c1644e3dSJohn Hsu regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
727c1644e3dSJohn Hsu /* FLL 10-bit integer input */
728c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL3,
729c1644e3dSJohn Hsu NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
730c1644e3dSJohn Hsu /* FLL pre-scaler */
731c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL4,
732c1644e3dSJohn Hsu NAU8540_FLL_REF_DIV_MASK,
733c1644e3dSJohn Hsu fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
734c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL5,
735c1644e3dSJohn Hsu NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
736c1644e3dSJohn Hsu regmap_update_bits(regmap,
737c1644e3dSJohn Hsu NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
738c1644e3dSJohn Hsu if (fll_param->fll_frac) {
739c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL5,
740c1644e3dSJohn Hsu NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
741c1644e3dSJohn Hsu NAU8540_FLL_FTR_SW_MASK,
742c1644e3dSJohn Hsu NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
743c1644e3dSJohn Hsu NAU8540_FLL_FTR_SW_FILTER);
744c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL6,
745fe83b1b7SJohn Hsu NAU8540_SDM_EN | NAU8540_CUTOFF500,
746fe83b1b7SJohn Hsu NAU8540_SDM_EN | NAU8540_CUTOFF500);
747c1644e3dSJohn Hsu } else {
748c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL5,
749c1644e3dSJohn Hsu NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
750c1644e3dSJohn Hsu NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
751fe83b1b7SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL6,
752fe83b1b7SJohn Hsu NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
753c1644e3dSJohn Hsu }
754c1644e3dSJohn Hsu }
755c1644e3dSJohn Hsu
756c1644e3dSJohn Hsu /* freq_out must be 256*Fs in order to achieve the best performance */
nau8540_set_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)757415bc3a0SKuninori Morimoto static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source,
758c1644e3dSJohn Hsu unsigned int freq_in, unsigned int freq_out)
759c1644e3dSJohn Hsu {
760415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
761c1644e3dSJohn Hsu struct nau8540_fll fll_param;
762c1644e3dSJohn Hsu int ret, fs;
763c1644e3dSJohn Hsu
764c1644e3dSJohn Hsu switch (pll_id) {
765c1644e3dSJohn Hsu case NAU8540_CLK_FLL_MCLK:
766c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
767fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
768fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MCLK | 0);
769c1644e3dSJohn Hsu break;
770c1644e3dSJohn Hsu
771c1644e3dSJohn Hsu case NAU8540_CLK_FLL_BLK:
772c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
773fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
774fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_BLK |
775fe83b1b7SJohn Hsu (0xf << NAU8540_GAIN_ERR_SFT));
776c1644e3dSJohn Hsu break;
777c1644e3dSJohn Hsu
778c1644e3dSJohn Hsu case NAU8540_CLK_FLL_FS:
779c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
780fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
781fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_FS |
782fe83b1b7SJohn Hsu (0xf << NAU8540_GAIN_ERR_SFT));
783c1644e3dSJohn Hsu break;
784c1644e3dSJohn Hsu
785c1644e3dSJohn Hsu default:
786c1644e3dSJohn Hsu dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
787c1644e3dSJohn Hsu return -EINVAL;
788c1644e3dSJohn Hsu }
789c1644e3dSJohn Hsu dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
790c1644e3dSJohn Hsu freq_out, pll_id);
791c1644e3dSJohn Hsu
792c1644e3dSJohn Hsu fs = freq_out / 256;
793c1644e3dSJohn Hsu ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
794c1644e3dSJohn Hsu if (ret < 0) {
795c1644e3dSJohn Hsu dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
796c1644e3dSJohn Hsu return ret;
797c1644e3dSJohn Hsu }
798c1644e3dSJohn Hsu dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
799c1644e3dSJohn Hsu fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
800c1644e3dSJohn Hsu fll_param.fll_int, fll_param.clk_ref_div);
801c1644e3dSJohn Hsu
802c1644e3dSJohn Hsu nau8540_fll_apply(nau8540->regmap, &fll_param);
803c1644e3dSJohn Hsu mdelay(2);
804c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
805c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
806c1644e3dSJohn Hsu
807c1644e3dSJohn Hsu return 0;
808c1644e3dSJohn Hsu }
809c1644e3dSJohn Hsu
nau8540_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)810415bc3a0SKuninori Morimoto static int nau8540_set_sysclk(struct snd_soc_component *component,
811c1644e3dSJohn Hsu int clk_id, int source, unsigned int freq, int dir)
812c1644e3dSJohn Hsu {
813415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
814c1644e3dSJohn Hsu
815c1644e3dSJohn Hsu switch (clk_id) {
816c1644e3dSJohn Hsu case NAU8540_CLK_DIS:
817c1644e3dSJohn Hsu case NAU8540_CLK_MCLK:
818c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
819c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
820c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
821c1644e3dSJohn Hsu NAU8540_DCO_EN, 0);
822c1644e3dSJohn Hsu break;
823c1644e3dSJohn Hsu
824c1644e3dSJohn Hsu case NAU8540_CLK_INTERNAL:
825c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
826c1644e3dSJohn Hsu NAU8540_DCO_EN, NAU8540_DCO_EN);
827c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
828c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
829c1644e3dSJohn Hsu break;
830c1644e3dSJohn Hsu
831c1644e3dSJohn Hsu default:
832c1644e3dSJohn Hsu dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
833c1644e3dSJohn Hsu return -EINVAL;
834c1644e3dSJohn Hsu }
835c1644e3dSJohn Hsu
836c1644e3dSJohn Hsu dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
837c1644e3dSJohn Hsu freq, clk_id);
838c1644e3dSJohn Hsu
839c1644e3dSJohn Hsu return 0;
840c1644e3dSJohn Hsu }
841c1644e3dSJohn Hsu
nau8540_reset_chip(struct regmap * regmap)842c1644e3dSJohn Hsu static void nau8540_reset_chip(struct regmap *regmap)
843c1644e3dSJohn Hsu {
844c1644e3dSJohn Hsu regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
845c1644e3dSJohn Hsu regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
846c1644e3dSJohn Hsu }
847c1644e3dSJohn Hsu
nau8540_init_regs(struct nau8540 * nau8540)848c1644e3dSJohn Hsu static void nau8540_init_regs(struct nau8540 *nau8540)
849c1644e3dSJohn Hsu {
850c1644e3dSJohn Hsu struct regmap *regmap = nau8540->regmap;
851c1644e3dSJohn Hsu
852c1644e3dSJohn Hsu /* Enable Bias/VMID/VMID Tieoff */
853c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
854c1644e3dSJohn Hsu NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
855c1644e3dSJohn Hsu NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
856c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
857c1644e3dSJohn Hsu NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
858c1644e3dSJohn Hsu NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
859c1644e3dSJohn Hsu mdelay(2);
860c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
861c1644e3dSJohn Hsu NAU8540_PU_PRE, NAU8540_PU_PRE);
862c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
863c1644e3dSJohn Hsu NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
864c1644e3dSJohn Hsu NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
865e4d0db60SJohn Hsu /* ADC OSR selection, CLK_ADC = Fs * OSR;
866e4d0db60SJohn Hsu * Channel time alignment enable.
867e4d0db60SJohn Hsu */
868c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
869e4d0db60SJohn Hsu NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
870e4d0db60SJohn Hsu NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
87114323ff8SJohn Hsu /* PGA input mode selection */
87214323ff8SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
87314323ff8SJohn Hsu NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
87414323ff8SJohn Hsu NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
87514323ff8SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
87614323ff8SJohn Hsu NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
87714323ff8SJohn Hsu NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
8786573c051SJohn Hsu /* DO12 and DO34 pad output disable */
8796573c051SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
8806573c051SJohn Hsu NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
8816573c051SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
8826573c051SJohn Hsu NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
883c1644e3dSJohn Hsu }
884c1644e3dSJohn Hsu
nau8540_suspend(struct snd_soc_component * component)885415bc3a0SKuninori Morimoto static int __maybe_unused nau8540_suspend(struct snd_soc_component *component)
886c1644e3dSJohn Hsu {
887415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
888c1644e3dSJohn Hsu
889c1644e3dSJohn Hsu regcache_cache_only(nau8540->regmap, true);
890c1644e3dSJohn Hsu regcache_mark_dirty(nau8540->regmap);
891c1644e3dSJohn Hsu
892c1644e3dSJohn Hsu return 0;
893c1644e3dSJohn Hsu }
894c1644e3dSJohn Hsu
nau8540_resume(struct snd_soc_component * component)895415bc3a0SKuninori Morimoto static int __maybe_unused nau8540_resume(struct snd_soc_component *component)
896c1644e3dSJohn Hsu {
897415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
898c1644e3dSJohn Hsu
899c1644e3dSJohn Hsu regcache_cache_only(nau8540->regmap, false);
900c1644e3dSJohn Hsu regcache_sync(nau8540->regmap);
901c1644e3dSJohn Hsu
902c1644e3dSJohn Hsu return 0;
903c1644e3dSJohn Hsu }
904c1644e3dSJohn Hsu
905415bc3a0SKuninori Morimoto static const struct snd_soc_component_driver nau8540_component_driver = {
906c1644e3dSJohn Hsu .set_sysclk = nau8540_set_sysclk,
907c1644e3dSJohn Hsu .set_pll = nau8540_set_pll,
908c1644e3dSJohn Hsu .suspend = nau8540_suspend,
909c1644e3dSJohn Hsu .resume = nau8540_resume,
910c1644e3dSJohn Hsu .controls = nau8540_snd_controls,
911c1644e3dSJohn Hsu .num_controls = ARRAY_SIZE(nau8540_snd_controls),
912c1644e3dSJohn Hsu .dapm_widgets = nau8540_dapm_widgets,
913c1644e3dSJohn Hsu .num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets),
914c1644e3dSJohn Hsu .dapm_routes = nau8540_dapm_routes,
915c1644e3dSJohn Hsu .num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes),
916415bc3a0SKuninori Morimoto .suspend_bias_off = 1,
917415bc3a0SKuninori Morimoto .idle_bias_on = 1,
918415bc3a0SKuninori Morimoto .use_pmdown_time = 1,
919415bc3a0SKuninori Morimoto .endianness = 1,
920c1644e3dSJohn Hsu };
921c1644e3dSJohn Hsu
922c1644e3dSJohn Hsu static const struct regmap_config nau8540_regmap_config = {
923c1644e3dSJohn Hsu .val_bits = 16,
924c1644e3dSJohn Hsu .reg_bits = 16,
925c1644e3dSJohn Hsu
926c1644e3dSJohn Hsu .max_register = NAU8540_REG_MAX,
927c1644e3dSJohn Hsu .readable_reg = nau8540_readable_reg,
928c1644e3dSJohn Hsu .writeable_reg = nau8540_writeable_reg,
929c1644e3dSJohn Hsu .volatile_reg = nau8540_volatile_reg,
930c1644e3dSJohn Hsu
931c1644e3dSJohn Hsu .cache_type = REGCACHE_RBTREE,
932c1644e3dSJohn Hsu .reg_defaults = nau8540_reg_defaults,
933c1644e3dSJohn Hsu .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
934c1644e3dSJohn Hsu };
935c1644e3dSJohn Hsu
nau8540_i2c_probe(struct i2c_client * i2c)9367325ed4dSStephen Kitt static int nau8540_i2c_probe(struct i2c_client *i2c)
937c1644e3dSJohn Hsu {
938c1644e3dSJohn Hsu struct device *dev = &i2c->dev;
939c1644e3dSJohn Hsu struct nau8540 *nau8540 = dev_get_platdata(dev);
940c1644e3dSJohn Hsu int ret, value;
941c1644e3dSJohn Hsu
942c1644e3dSJohn Hsu if (!nau8540) {
943c1644e3dSJohn Hsu nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
944c1644e3dSJohn Hsu if (!nau8540)
945c1644e3dSJohn Hsu return -ENOMEM;
946c1644e3dSJohn Hsu }
947c1644e3dSJohn Hsu i2c_set_clientdata(i2c, nau8540);
948c1644e3dSJohn Hsu
949c1644e3dSJohn Hsu nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
950c1644e3dSJohn Hsu if (IS_ERR(nau8540->regmap))
951c1644e3dSJohn Hsu return PTR_ERR(nau8540->regmap);
952c1644e3dSJohn Hsu ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
953c1644e3dSJohn Hsu if (ret < 0) {
954c1644e3dSJohn Hsu dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
955c1644e3dSJohn Hsu ret);
956c1644e3dSJohn Hsu return ret;
957c1644e3dSJohn Hsu }
958c1644e3dSJohn Hsu
959c1644e3dSJohn Hsu nau8540->dev = dev;
960c1644e3dSJohn Hsu nau8540_reset_chip(nau8540->regmap);
961c1644e3dSJohn Hsu nau8540_init_regs(nau8540);
962c1644e3dSJohn Hsu
963415bc3a0SKuninori Morimoto return devm_snd_soc_register_component(dev,
964415bc3a0SKuninori Morimoto &nau8540_component_driver, &nau8540_dai, 1);
965c1644e3dSJohn Hsu }
966c1644e3dSJohn Hsu
967c1644e3dSJohn Hsu static const struct i2c_device_id nau8540_i2c_ids[] = {
968*ba2a2c37SUwe Kleine-König { "nau8540" },
969c1644e3dSJohn Hsu { }
970c1644e3dSJohn Hsu };
971c1644e3dSJohn Hsu MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
972c1644e3dSJohn Hsu
973c1644e3dSJohn Hsu #ifdef CONFIG_OF
974c1644e3dSJohn Hsu static const struct of_device_id nau8540_of_ids[] = {
975c1644e3dSJohn Hsu { .compatible = "nuvoton,nau8540", },
976c1644e3dSJohn Hsu {}
977c1644e3dSJohn Hsu };
978c1644e3dSJohn Hsu MODULE_DEVICE_TABLE(of, nau8540_of_ids);
979c1644e3dSJohn Hsu #endif
980c1644e3dSJohn Hsu
981c1644e3dSJohn Hsu static struct i2c_driver nau8540_i2c_driver = {
982c1644e3dSJohn Hsu .driver = {
983c1644e3dSJohn Hsu .name = "nau8540",
984c1644e3dSJohn Hsu .of_match_table = of_match_ptr(nau8540_of_ids),
985c1644e3dSJohn Hsu },
9869abcd240SUwe Kleine-König .probe = nau8540_i2c_probe,
987c1644e3dSJohn Hsu .id_table = nau8540_i2c_ids,
988c1644e3dSJohn Hsu };
989c1644e3dSJohn Hsu module_i2c_driver(nau8540_i2c_driver);
990c1644e3dSJohn Hsu
991c1644e3dSJohn Hsu MODULE_DESCRIPTION("ASoC NAU85L40 driver");
992c1644e3dSJohn Hsu MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
993c1644e3dSJohn Hsu MODULE_LICENSE("GPL v2");
994